FinFET device-based full-swing single-end read storage unit

Abstract

The invention discloses a FinFET device-based full-swing single-end read storage unit. The unit comprises a write word line, a writ bit line, an inverted write bit line, a read word line, a read bit line, a first FinFET, a second FinFET, a third FinFET, a fourth FinFET, a fifth FinFET, a sixth FinFET, a seventh FinFET, an eighth FinFET and a ninth FinFET, wherein the first FinFET, the second FinFET and the seventh FinFET are low-threshold P-type FinFETs; the third FinFET, the fourth FinFET, the fifth FinFET, the sixth FinFET and the ninth FinFET are low-threshold N-type FinFETs; and the eighth FinFET is a high-threshold N-type FinFET. The unit has the advantages that under the condition of not influencing a circuit function, the delay, the power consumption and a power-delay product are all relatively small, a data error does not occur during read operation, and the circuit stability is relatively high.

Description

technical field [0001] The invention relates to a storage unit, in particular to a full-swing single-end read storage unit based on a FinFET device. Background technique [0002] As the process size enters the nanometer level, power consumption has become a problem that IC designers have to pay attention to. In most digital systems, memory power consumption accounts for an increasing proportion of total circuit power consumption. Static Random Access Memory (SRAM, Static Random Access Memory) is an important component in memory, so it is of great research significance to design SRAM with high stability and low power consumption. The SRAM is mainly composed of a storage array and other peripheral circuits, and the storage array is composed of a storage unit, which is the core of the SRAM, and the performance of the storage unit directly determines the performance of the SRAM. [0003] As the size of transistors continues to shrink, limited by the short-channel effect and th...

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Problems solved by technology

The storage unit may destroy the data value stored in the storage point during the read operation. At the same time, due to the voltage division of the bit line capacitance in the read operation, the voltage may be compressed during the read. If the compression is too large, the read data will be just right. Contrary to storing data, this leads to data errors during read operations, and the circuit function is unstable; moreover, the pull-down network composed of FINFET tube M3 and FINFET tube M4 has two paths of leakage current when the storage unit is in the holding state, so the leakage current The current is large, which leads to large leakage power consumption and large delay, which is not conducive to fast and stable data access

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