FinFET device-based full-swing single-end read storage unit

A storage unit, full swing technology, applied in information storage, static memory, digital memory information and other directions, can solve the problems of unstable circuit function, large delay, destroying the data value of the storage point, etc., to improve the sensitivity and improve the noise. The effect of tolerance

Active Publication Date: 2017-11-24
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The storage unit may destroy the data value stored in the storage point during the read operation. At the same time, due to the voltage division of the bit line capacitance in the read operation, the voltage may be compressed during the read. If the compression is too large, the read data will be just right. Contrary to storing data, this leads to data errors during rea

Method used

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  • FinFET device-based full-swing single-end read storage unit
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  • FinFET device-based full-swing single-end read storage unit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0015] Embodiment one: if figure 2As shown, a read decoupling memory unit based on a FinFET device includes a write word line WWL, a write bit line WBL, an inverted write bit line WBLb, a read word line RWL, a read bit line RBL, a first FinFET tube B1, a second FinFET B2, third FinFET B3, fourth FinFET B4, fifth FinFET B5, sixth FinFET B6, seventh FinFET B7, eighth FinFET B8, ninth FinFET B9, first FinFET B1, the second FinFET tube B2 and the seventh FinFET tube B7 are respectively low-threshold P-type FinFET tubes, the third FinFET tube B3, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6 and the ninth FinFET tube Tube B9 is an N-type FinFET tube with a low threshold, the eighth FinFET tube B8 is an N-type FinFET tube with a high threshold, the source of the first FinFET B1, the source of the second FinFET B2, and the seventh FinFET B7 The source of the read decoupling storage unit is connected to the power supply terminal of the read decoupling...

Embodiment 2

[0016] Embodiment two: if figure 2 As shown, a read decoupling memory unit based on a FinFET device includes a write word line WWL, a write bit line WBL, an inverted write bit line WBLb, a read word line RWL, a read bit line RBL, a first FinFET tube B1, a second FinFET B2, third FinFET B3, fourth FinFET B4, fifth FinFET B5, sixth FinFET B6, seventh FinFET B7, eighth FinFET B8, ninth FinFET B9, first FinFET B1, the second FinFET tube B2 and the seventh FinFET tube B7 are respectively low-threshold P-type FinFET tubes, the third FinFET tube B3, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6 and the ninth FinFET tube Tube B9 is an N-type FinFET tube with a low threshold, the eighth FinFET tube B8 is an N-type FinFET tube with a high threshold, the source of the first FinFET B1, the source of the second FinFET B2, and the seventh FinFET B7 The source of the read decoupling storage unit is connected to the power supply terminal of the read decouplin...

Embodiment 3

[0018] Embodiment three: as figure 2 As shown, a read decoupling memory unit based on a FinFET device includes a write word line WWL, a write bit line WBL, an inverted write bit line WBLb, a read word line RWL, a read bit line RBL, a first FinFET tube B1, a second FinFET B2, third FinFET B3, fourth FinFET B4, fifth FinFET B5, sixth FinFET B6, seventh FinFET B7, eighth FinFET B8, ninth FinFET B9, first FinFET B1, the second FinFET tube B2 and the seventh FinFET tube B7 are respectively low-threshold P-type FinFET tubes, the third FinFET tube B3, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6 and the ninth FinFET tube Tube B9 is an N-type FinFET tube with a low threshold, the eighth FinFET tube B8 is an N-type FinFET tube with a high threshold, the source of the first FinFET B1, the source of the second FinFET B2, and the seventh FinFET B7 The source of the read decoupling storage unit is connected to the power supply terminal of the read decoupl...

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PUM

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Abstract

The invention discloses a FinFET device-based full-swing single-end read storage unit. The unit comprises a write word line, a writ bit line, an inverted write bit line, a read word line, a read bit line, a first FinFET, a second FinFET, a third FinFET, a fourth FinFET, a fifth FinFET, a sixth FinFET, a seventh FinFET, an eighth FinFET and a ninth FinFET, wherein the first FinFET, the second FinFET and the seventh FinFET are low-threshold P-type FinFETs; the third FinFET, the fourth FinFET, the fifth FinFET, the sixth FinFET and the ninth FinFET are low-threshold N-type FinFETs; and the eighth FinFET is a high-threshold N-type FinFET. The unit has the advantages that under the condition of not influencing a circuit function, the delay, the power consumption and a power-delay product are all relatively small, a data error does not occur during read operation, and the circuit stability is relatively high.

Description

technical field [0001] The invention relates to a storage unit, in particular to a full-swing single-end read storage unit based on a FinFET device. Background technique [0002] As the process size enters the nanometer level, power consumption has become a problem that IC designers have to pay attention to. In most digital systems, memory power consumption accounts for an increasing proportion of total circuit power consumption. Static Random Access Memory (SRAM, Static Random Access Memory) is an important component in memory, so it is of great research significance to design SRAM with high stability and low power consumption. The SRAM is mainly composed of a storage array and other peripheral circuits, and the storage array is composed of a storage unit, which is the core of the SRAM, and the performance of the storage unit directly determines the performance of the SRAM. [0003] As the size of transistors continues to shrink, limited by the short-channel effect and th...

Claims

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Application Information

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IPC IPC(8): G11C11/412G11C11/419
Inventor 胡建平杨会山
Owner NINGBO UNIV
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