Manufacturing method of planar VDMOS device

Abstract

The invention provides a manufacturing method of a planar VDMOS device. The method comprises the steps of performing photoetching and etching on a polysilicon layer on a gate oxidation layer, and forming a gate electrode on an intermediate area above the gate oxidation layer, wherein the width of the cross section of the gate electrode is A+X micrometers; manufacturing a P- region of a planar VDMOS device; on the condition of blocking by the gate electrode, manufacturing a P+ deep region of the planar VDMOS device so that the diffusion width of the P+ deep region is X micrometers; converting the polysilicon outside the gate electrode to an oxide layer by means of a low-temperature oxidation process, wherein the thickness of the oxide layer is X / 2 micrometers so that the boundary of the gate electrode is level to the corresponding boundary of the P+ deep region; eliminating the oxide layer outside the gate electrode and the gate oxide layer at the left side and the right side of the gate electrode; and using the gate electrode as a blocking member, performing self-aligned N+ source region injection and driving, thereby forming an N+ source region. The P+ deep region does not affect the channel, thereby realizing higher device stability, obtaining the deep region with large junction depth and obtaining better EAS capability of the device.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductor fabrication, and in particular to a fabrication method of a planar VDMOS device. Background technique [0002] Single-pulse avalanche energy (abbreviated as EAS) is a very important parameter of a planar VDMOS device, which is the maximum energy that the device can consume in a single avalanche state. In the application environment where the source and drain will generate large voltage spikes, the single-pulse avalanche energy of the device must be considered. [0003] Since the planar VDMOS device itself has a parasitic transistor between the epitaxial layer-body region-source region, when the device is turned off, when the reverse current between the source and drain flows through the body region, a voltage drop will occur. If the generated voltage drop is greater than the turn-on voltage of the parasitic triode, the reverse current will turn on the parasitic triode ...

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Problems solved by technology

However, since the temperature driving into the P+ deep body region will also drive into the N+ source region, it is easy to reduce the channel length, resulting in short channel effect

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