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A method and system for ensuring data crash consistency

A consistency and data technology, applied in the input/output process of data processing, electrical digital data processing, instruments, etc., can solve the problems of increasing user request response delay and reducing system performance, so as to avoid system delay and reduce Response delay, impact reduction effect

Active Publication Date: 2019-05-14
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the existing technology of ensuring data crash consistency through log technology increases the response delay to user requests and reduces the performance of the entire system

Method used

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  • A method and system for ensuring data crash consistency
  • A method and system for ensuring data crash consistency
  • A method and system for ensuring data crash consistency

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Embodiment Construction

[0041] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0042] figure 1 A schematic flowchart of a method for ensuring data crash consistency provided by an embodiment of the present invention, the method is applicable to a storage system including a non-volatile cache memory and a non-volatile memory storage, such as figure 1 As shown, steps S101 to S104 are included.

[0043] In step S101, determine the write frequency of the first cache line corresponding to the write operation address of the write request. Matching cache lines, the old valid data at the address of the write operation exists in the first cache line, the write request belongs to ...

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Abstract

The invention discloses a method and system for ensuring data crash consistency. The method includes the steps that the writing frequency of a first cache line corresponding to a write request is determined; when the writing frequency of the first cache line is larger than or equal to a threshold, data corresponding to the write request is written in a second cache line of a nonvolatile cache memory; when the writing frequency of the first cache line is smaller than the threshold, the data in the first cache line is migrated into a nonvolatile memory, and after the data of the first cache line is migrated, data corresponding to the write request is written in the first cache line; when a memory transaction where the write request belongs is completed, the data in the first cache line is marked as invalid data and the data in the second cache line is marked as new valid data if the data of the first cache line is not migrated; if the data of the first cache line is migrated, the data in the first cache line is marked as new valid data. By means of the method and system, the number of times of writing operation on the relatively slow nonvolatile memory is reduced, and the performance of a storage system is improved.

Description

technical field [0001] The invention belongs to the technical field of computer storage, and more specifically relates to a method and system for ensuring data crash consistency. Background technique [0002] With the development of computer multi-core technology and computer application technology, the demand for memory in current applications is increasing. The traditional dynamic random access memory (Dynamic Random Access Memory, DRAM) has been Unable to keep up with increasing memory requirements of applications. The new non-volatile memory (Non-Volatile Memory, NVM) has become an ideal storage medium to replace DRAM to provide large memory because of its read and write speed close to DRAM, low standby power consumption, and strong scalability. However, compared with traditional DRAM memory, non-volatile memory cannot directly replace DRAM as memory due to its shortcomings such as limited read and write times, long read and write delay, and high energy consumption for ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
CPCG06F3/0619G06F3/0631G06F3/0647G06F3/0656G06F3/0679
Inventor 童薇刘景宁冯丹马骏魏学亮
Owner HUAZHONG UNIV OF SCI & TECH
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