Sub-matrix operation device and method

Abstract

The invention provides a sub-matrix operation device and method. The device includes a storage unit, a register unit and a sub-matrix operation unit. Sub-matrix data are stored in the storage unit. Sub-matrix information is stored in the register unit. The sub-matrix operation unit acquires the sub-matrix information in the register unit according to a sub-matrix operation instruction, acquires the corresponding sub-matrix data in the storage unit according to the sub-matrix information, and then carries out sub-matrix operations according to the acquired sub-matrix data to obtain a sub-matrix operation result. According to the device and method, the sub-matrix data involved in computation is temporarily stored on a high-speed scratchpad memory, the device can be enabled to more flexibly and effectively support data with different widths in sub-matrix operation processes, and the execution performance of a computation task including a large number of sub-matrices is improved.

Description

technical field [0001] The invention belongs to the field of computers, and in particular relates to a sub-matrix operation device and method, which are used for obtaining sub-matrix data from matrix data according to sub-matrix operation instructions, and performing sub-matrix operations according to the sub-matrix data. Background technique [0002] At present, more and more algorithms in the computer field involve matrix operations, including artificial neural network algorithms and graphics rendering algorithms. At the same time, as an important part of matrix operations, submatrix operations appear more and more frequently in various computing tasks. Therefore, for those schemes oriented to solving matrix operation problems, the efficiency and difficulty of sub-matrix operation implementation must be considered at the same time. [0003] A known solution in the prior art to perform sub-matrix operations is to use a general-purpose processor, which executes general-purp...

AI Technical Summary

Problems solved by technology

However, currently existing dedicated matrix operation devices are limited by register files and cannot flexibly support sub-matrix operations of different lengths

[0006] In summary, no matter the existing multi-core general-purpose processors on-chip, inter-chip interconnection general-purpose processors (single-core or multi-core), or inter-chip interconnections, graphics processors cannot perform efficient sub-matrix operations, and these existing When dealing with sub-matrix operations, there are problems such as a large amount of code, limited inter-chip communication, insufficient on-chip cache, and insufficient flexibility in the size of the supported sub-matrix.

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