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High-resolution image acquisition and processing device

A high-resolution image and processing device technology, applied in the field of high-resolution image acquisition and processing devices, can solve the problems of poor flexibility, poor applicability, and poor real-time processing ability, and achieve the effect of good flexibility

Active Publication Date: 2017-10-13
ZHEJIANG UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to overcome the deficiencies of existing image processing devices, such as poor real-time processing capability, poor applicability, and poor flexibility for high-resolution images, the present invention provides a real-time processing high-resolution image with good applicability and flexibility. Higher resolution image acquisition and processing device

Method used

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  • High-resolution image acquisition and processing device

Examples

Experimental program
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Effect test

Embodiment 1

[0060] like Figure 4 As shown, it is a block diagram of FPGA internal functions. The main modules include lvds_video_rx module serial-to-parallel conversion module A, signal mapping rx_signal_mapping module B, cropping module C, and multi-channel synchronization module D.

[0061] The lvds_video_rx module A is mainly completed by the IP core provided by the FPGA supplier, such as the iddrx core of Lattice and the atllvds core of Altera. Since the differential data transmission paths of each channel are different (such as the length of PCB traces, etc.), transmission delays between channels will eventually occur. Therefore, the bit stream transmitted by each differential channel must be resolved separately according to the LVDS video transmission protocol. String, this module is to realize the deserialization of a single channel, output multiple channels of parallel data, and determine the data width such as 8bit or 10bit according to the configuration of the sensor.

[0062]...

Embodiment 2

[0113] Embodiment 2 is mainly aimed at the acquisition and preprocessing of ultra-high resolution images, and there is a discrepancy with Embodiment 1 mainly in the cropping unit and timing control unit.

[0114] For the acquisition and processing of ultra-high resolution images, due to its large data throughput, the required parallel pixel synchronization clock is also large. Therefore, for FPGAs that cannot support high read / write rate FIFOs internally, the principle of area speed exchange needs to be adopted.

[0115] like Figure 11 As shown, the larger logic that was originally completed in one clock cycle is reasonably cut and completed in multiple clock cycles, and multiple times of logic resources are used to achieve the same function, thereby meeting the data throughput requirements. In this system, each asynchronous FIFO unit in the first embodiment needs to be replaced by y synchronous FIFOs, that is, s×y synchronous FIFOs are required to replace s asynchronous FIFO...

Embodiment 3

[0126] Embodiment 3 is similar to Embodiment 1, in that s asynchronous FIFOs are used to buffer data in different clock domains, and there is a discrepancy between the timing control unit and Embodiment 1 mainly. The first implementation mode is to perform write-while-read operations on s asynchronous FIFOs, and the third implementation mode adopts the mode of writing first and then reading.

[0127] The specific implementation process of embodiment 3 is as follows:

[0128] First, with w_clk (equal to f p ) Write the data of the first channel of the row that needs to be trimmed into the asynchronous FIFO. At this time, the read enable is set to invalid, and then the data of the second channel of the row is written in succession, ... until the sth channel of the row is written For the first data, the read operation is enabled for the s asynchronous FIFOs at the same time, and the image data of the s channels of the row is read out at the same time, so as to ensure the synchro...

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Abstract

The invention relates to a high-resolution image acquisition and processing device. The device includes an image acquisition module, an LVDS (Low Voltage Differential Signaling) serial-to-parallel conversion module, a data mapping module, an image cutting module, a multi-path synchronization module, a communication control module, an image processing module, an output display module and peripherals; the LVDS serial-to-parallel conversion module is used for deserializing the data of each channel of an LVDS (Low Voltage Differential Signaling) interface, recovering clock signals from serial data streams and demodulating the restored data; the data mapping module is used for performing alignment, data frame decoding and combinational mapping operation on bit data which are analyzed from the differential channels; the image cutting module is used for analyzing and cutting high-resolution images and outputting a plurality of paths of small-frame images; and a multi-path synchronization module is used for performing synchronization operation on the plurality of paths of small-frame images and transmitting the synchronized image data to the video input interface of a main processor in parallel at the same time. The high-resolution image acquisition and processing device of the invention has the advantages of real-time processing of high-resolution images, high applicability and high flexibility.

Description

technical field [0001] The invention relates to related fields such as image processing, security protection, and video monitoring, and in particular to a high-resolution image acquisition and processing device. Background technique [0002] With the continuous development of computer vision and image processing technology and the expansion of its application fields, people's demand for high-resolution and high-definition video / image is also increasing. As we all know, fixed-resolution images will be distorted after multi-stage amplification. Researchers generally have a variety of improvement solutions for this situation. The first solution is that the resolution of the images collected by the front end is fixed. In the back-end processing, measures such as improving the interpolation algorithm are taken to make the image continue to a certain extent and keep the image distortion within a tolerable range, but the disadvantage of this method is that when the image continues ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N5/232
CPCH04N23/60H04N23/80
Inventor 郑雅羽张亮亮陈超
Owner ZHEJIANG UNIV OF TECH
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