Device and method for realizing automatic reading and writing test of ddr interface based on fpga

Abstract

The invention discloses a device and method based on FPGA for achieving automatic read-write testing of a DDR interface. The method includes the steps of converting a read / write configuration file issued by a CPU to a DMA instruction, and successively dividing the DMA instruction into multiple read / write instructions; converting the instructions into a read / write operation matched with the DDR controller user interface, wherein a user-defined format matched with the memory address of the DDR controller user interface is adopted as a write data format; detecting read-back data which are already written into a data interface to conduct read operation; if the read-back data is not in accordance with read-in data, recording the cumulative number of reading errors; after testing is finished, sending the cumulative number of the reading errors, starting timestamp and ending timestamp to the CPU; according to the starting timestamp and the ending timestamp, calculating testing duration; according to the testing duration and automatic testing length, calculating read / write speed. According to the device and method based on the FPGA for achieving automatic read-write testing of the DDR interface, the read testing of a high-capacity device, can be fast and high-effectively completed, and the accuracy of the test value of read-write speed is greatly improved.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a device and a method for realizing automatic reading and writing testing of DDR (Dual Data Rate, double-rate synchronous dynamic random access memory) based on FPGA (Field Programmable Gate Array, Field Programmable Gate Array). Background technique [0002] DDR was released by JEDEC (Joint Electronic Device Engineering Committee) in 2004. It has experienced the development of DDR, DDR2, DDR3, and DDR4. DDR is widely used in data communication with high storage requirements due to its advantages of low cost, large capacity, and high speed. field. [0003] The DDR system usually consists of a DDR controller and a DDR memory. The DDR controller initiates instructions such as initialization, reading or writing to the DDR memory according to the timing defined in the DDR specification according to the user's request. DDR memory is used to store data and respond to instructions fro...

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Problems solved by technology

[0005] The technical problem to be solved by the present invention is that in the existing FPGA-based DDR controller design, the mode of using CPU to execute read and write commands is used to test the DDR controller user interface, which has the defects of long test period and inaccurate test data

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