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Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and method of making the same

A technology for semiconductors and heat sinks, which is used in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc.

Inactive Publication Date: 2017-10-03
BRIDGE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The main purpose of the present invention is to provide a semiconductor component, in which the semiconductor element is electrically coupled to the interconnection substrate through a plurality of bumps, so as to solve the alignment problem between the semiconductor element and the interconnection substrate, and avoid the I / O of the element Directly use laser or optical imaging process on the pad to improve the production yield and reliability of semiconductor components

Method used

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  • Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and method of making the same
  • Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and method of making the same
  • Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and method of making the same

Examples

Experimental program
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Embodiment 1

[0103] Figure 1-26 It is a diagram of a manufacturing method of a semiconductor component in the first embodiment of the present invention, which includes a semiconductor element 13 , a heat sink 20 , a first build-up circuit 110 and a second build-up circuit 310 .

[0104] figure 1 is a cross-sectional view of the first contact pad 113 deposited on the sacrificial carrier 111 . The sacrificial carrier 111 is generally made of any conductive or non-conductive material, such as copper, nickel, aluminum, chromium, tin, iron, stainless steel, silicon, glass, graphite, plastic film, or other metals, alloys or non-metallic materials. The thickness of the sacrificial carrier 111 is preferably 0.1 to 10 mm. In this embodiment, the sacrificial carrier 111 is made of ferrous material and has a thickness of 1.0 mm. The first contact pads 113 are typically made of copper and can be patterned deposited by various techniques such as electroplating, electroless plating, evaporation, spu...

Embodiment 2

[0126] Figure 27-36 It is a diagram of another manufacturing method of a semiconductor device in the second embodiment of the present invention, wherein a positioning member is provided outside the cavity of the heat sink, and the heat sink is also electrically coupled to the second build-up circuit.

[0127] For the purpose of brief description, any descriptions in the above-mentioned embodiment 1 that can be used for the same application are incorporated here, and it is not necessary to repeat the same descriptions.

[0128] Figure 27It is a cross-sectional view of the heat sink 20 , which is provided with a positioning member 213 around the entrance of the cavity 211 . The positioning member 213 can be formed by removing a selected portion of the metal plate 21 , or by depositing a metal material or a plastic material by patterning on the metal plate 21 . The positioning member 213 is usually made by electroplating, etching, mechanical cutting or lamination steps. Acco...

Embodiment 3

[0140] Figure 37-46 It is a diagram of a manufacturing method of a semiconductor component using a laminated substrate as a heat sink in the third embodiment of the present invention.

[0141] For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are incorporated here, and the same descriptions do not need to be repeated.

[0142] Figure 37 and 38 It is a cross-sectional view of the manufacturing process of the positioning member according to an embodiment of the present invention, which is formed on the dielectric layer of the laminated substrate.

[0143] Figure 37 is a cross-sectional view of a laminated substrate, which includes a metal plate 21 , a dielectric layer 23 , and a metal layer 25 . The dielectric layer 23 is sandwiched between the metal plate 21 and the metal layer 25 . The dielectric layer 23 is generally made of epoxy, glass epoxy, polyimide, or the like, and has a thickness of 50 mic...

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Abstract

The present invention relates to methods of making a semiconductor assembly having a semiconductor device embedded in a heat spreader and electrically connected to a dual-stage formed interconnect substrate. In a preferred embodiment, the interconnect substrate consists of first and second build-up circuitries and the methods are characterized by the step of attaching a semiconductor subassembly having a first build-up circuitry adhered to a sacrificial carrier to a heat spreader using an adhesive with the semiconductor device inserted into a cavity of the heat spreader and the step of detaching the sacrificial carrier from the first build-up circuitry. The heat spreader provides thermal dissipation, and the first and second build-up circuitries provide staged fan-out routing for the semiconductor device.

Description

technical field [0001] The present invention relates to a heat dissipation-enhanced semiconductor component and its manufacturing method, especially to a heat-dissipation-enhanced semiconductor component, which embeds a semiconductor element in a heat sink and is electrically connected to a build-up circuit formed in two steps. Background technique [0002] In order to integrate mobile, communication, and computing functions, the semiconductor packaging industry is facing great challenges in heat dissipation, electrical properties, form-factor reduction, and reliability. Although many configurations of embedding semiconductor chips in circuit boards or molding materials have been reported in the literature, there are still many problems of insufficient performance. For example, the assemblies disclosed in U.S. Patent Nos. 8,742,589, 8,735,222, 8,679,963, 8,453,323, because the heat generated by the embedded chips in them cannot be dissipated properly by thermal insulating ma...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L23/367H01L23/498H01L23/544
CPCH01L21/4853H01L21/4882H01L23/3675H01L23/49816H01L23/544H01L2224/73253H01L23/5383H01L21/4857H01L21/78H01L2223/54426
Inventor 林文强王家忠
Owner BRIDGE SEMICON
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