Image sensor chip packaging structure and packaging method

Abstract

The invention provides an image sensor chip packaging structure and a packaging method. A chip back surface substrate groove etching process is adopted to avoid using a silicon piercing technology, the peripheral edge of a pad exposed at the bottom part of the groove is corrected to have a ladder-like structure, and thus, the filling difficulty of a wiring metal layer is reduced, the contact area between the subsequently-filled wiring metal layer and the pad is increased, and the wiring metal layer connection reliability is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a packaging structure and a packaging method of an image sensor chip. Background technique [0002] The CMOS image sensor (CMOS Image Sensor, CIS) is an important part of the digital camera. The principle of its imaging is to sense light through the photosensitive device, so as to convert the light signal into an electrical signal, and then output the image. [0003] Currently, mainstream CIS chip packaging technologies include: CSP (Chip Scale Package), COB (Chip On Board) and FC (Flip Chip). Among them, CSP refers to the chip packaging technology in which the chip size package and the core size of the chip are basically the same. It is currently widely used in Wafer level (wafer level) packaging of low-end, low-pixel (2M pixels or below) image sensors. CSP packaging technology generally uses the front of the image sensor chip as a photosensitive window, use...

AI Technical Summary

Problems solved by technology

However, due to the introduction of TSV interconnection in this wafer-level image sensor packaging method, the packaging structure is complicated; and TSV interconnection technology is still immature, often due to poor insulation in the hole, incomplete interconnection windows, and incomplete metal filling. Such problems lead to failure or poor reliability, which makes this kind of wafer-level image sensor packaging using through-silicon via interconnection have problems of high process difficulty and low interconnection reliability.

At the same time, the complexity of the through-silicon via interconnection process also makes the packaging price of the wafer-level image sensor using this technology relatively expensive.

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