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Fixed-point multiplying accumulator

A multiplication accumulator, fixed-point technology, applied in the field of fixed-point multiplication accumulator, can solve the problems of increasing the length of the critical path, performance degradation, etc., and achieve the effect of realizing the multiplication/accumulation/subtraction function, increasing the delay, and ensuring performance

Inactive Publication Date: 2017-06-27
青岛专用集成电路设计工程技术研究中心
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the existing technology, the saturation selection process is also performed after the multiplication result is obtained, and its disadvantage is still to increase the length of the critical path
[0013] In summary, if a multiplication accumulator needs to complete the above operations, it needs to add a multi-level selector to achieve it, and the multiplier is the key path of all computing units, and any increase in delay will lead to performance degradation

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] Embodiment 1. Fixed-point integer / decimal multiplication function:

[0041] This embodiment proposes a multiply-accumulator, which mainly includes a Booth coding unit, a left-shift logic unit, a Booth decoding / partial product generating unit, a compression tree, a compressor, an accumulator, an adder, etc., see figure 1 As shown, both fixed-point integer multiplication and fixed-point decimal multiplication can be realized without increasing the delay of multiply-accumulator.

[0042] The Booth encoding unit is used to perform Booth encoding on the multiplier.

[0043] Booth coding is used to reduce the number of partial products, and Booth coding with radix 4 can reduce the number of partial products by half. The following table is the encoding table of base 4Booth encoding:

[0044]

[0045] where X represents the multiplicand, x i Represents the bit with the multiplicand weight i, Y represents the multiplier, y 2t-1 Represents the bit weighted 2i-1 in the multip...

Embodiment 2

[0058] Embodiment 2. Multiply-accumulate / subtract function:

[0059] This embodiment proposes a multiply-accumulator, which mainly includes a Booth encoding unit, a Booth decoding / partial product generating unit, a compression tree, a compressor, an accumulator, an adder, etc., see Image 6 As shown, both the multiply-accumulate function and the multiply-accumulate-subtract function can be realized without increasing the delay of the multiply-accumulator.

[0060] The difference between the Booth coding unit in this embodiment and the first embodiment is that when performing a multiply-accumulate-subtract operation, the Booth coding unit performs Booth coding on the multiplier and then inverts the coding value neg to obtain a new Booth coding value neg_new; then use neg_new produces partial products, see Figure 7 shown.

[0061] Because the critical path of Booth encoding and decoding is the path where the encoded value b1 / b2 is located, the generation of Neg_new does not a...

Embodiment 3

[0072] Embodiment 3. Overflow judgment function:

[0073] In the prior art decimal multiplication, when two -1s are multiplied, saturation selection processing (overflow processing) is performed after the multiplication result is obtained, which has the disadvantage of increasing the length of the critical path.

[0074] In view of the above problem, if the multiply-accumulator needs to automatically saturate the multiplication result before accumulation, add operand judgment logic, and overflow only when both operands are -1. Therefore, this embodiment proposes a Multiply accumulator, mainly including Booth coding unit, Booth decoding / partial product generation unit, overflow judgment unit 1001, compression tree, compressor, accumulator, adder, etc., see Figure 9 As shown, the multiply-accumulate function and overflow judgment function are realized without increasing the length of the critical path.

[0075]The overflow judging unit 1001 is used to judge whether the multipl...

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Abstract

The invention discloses a fixed-point multiplying accumulator, which comprises a Booth coding unit, a left shift logic unit, a Booth decoding / partial product generation unit, a compression tree, a compressor and a summator, wherein the Booth coding unit is used for coding a multiplier; the left shift logic unit is used for enabling a multiplicand to leftwards shift for one bit to carry out lower-bit zero filling when the multiplicand is a decimal; the Booth decoding / partial product generation unit is used for generating partial products; the compression tree is used for compressing the partial products and outputting two piece of compressed data; the compressor is used for compressing data provided by the accumulator and the compression tree; and the summator is used for carrying out an addition operation on the data output by the compressor to output a result. By use of the fixed-point multiplying accumulator, fixed point integer / decimal multiplication, multiply-accumulation / subtraction functions and overflow judgment functions are realized, the time delay of a multiply-accumulator is not increased, and the performance of a processor is guaranteed.

Description

technical field [0001] The present invention relates to the technical field of processors, in particular to a fixed-point multiply-accumulator. Background technique [0002] The multiply operation is used in most algorithms, especially in signal processing algorithms, where the multiply-accumulate operation is one of the core operations, which makes it easy to measure the number of multiply-accumulate operations per second (MAC / S) performed by a digital signal processor. One of the indicators of computing power. Not only in digital signal processors, multipliers are also integrated in general-purpose processors, and some general-purpose processors also use multiply-accumulators in order to speed up image processing or other scientific calculations. [0003] In the prior art, the structure of a multiply-accumulator is usually the basic operation of multiplication using Booth coding and a compressed tree, and the value of the accumulator generally participates in the final co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/57
CPCG06F7/57
Inventor 周沈刚李任伟
Owner 青岛专用集成电路设计工程技术研究中心
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