Fractional-N phase locked loop circuit

Abstract

A fractional-N phase locked loop (PLL) circuit (104, 600, 800) is provided. The PLL circuit (104, 600, 800) generates a spread spectrum clock (SSC), using average techniques to suppress phase interpolator nonlinearity. The PLL circuit (600, 800) includes fractional dividers (606, 806) with hybrid finite impulse response (FIR) filtering. Furthermore, a small size and low power divider (606, 806) for a hybrid FIR fractional-N PLL circuit (600, 800) is provided.

Description

technical field [0001] Embodiments of the present invention relate to the field of electronic circuits, and in particular, to a fractional divider-type fractional-N phase-locked loop for a spread spectrum clock generator. Background technique [0002] Spread Spectrum Clock (SSC) signals are used in electronic components to help suppress electromagnetic interference. The SSC signal is clocked with different frequencies, typically oscillating between min / max values, according to the desired modulation shape function (eg, sine wave, triangle wave, etc.). The SSC signal can be generated by modulating the frequency of a clock signal generated by a Phase Locked Loop (PLL) circuit according to a predetermined modulation frequency and modulation angle. A sigma-delta modulator type fractional-N PLL can be used to generate the SSC signal; however, the quantization noise of the sigma-delta modulator can cause jitter to the PLL output. SUMMARY OF THE INVENTION [0003] Embodiments d...

AI Technical Summary

Problems solved by technology

A sigma-delta modulator type fractional-N PLL can be used to generate the SSC signal; however, the quantization noise of the sigma-delta modulator can cause jitter on the PLL output

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