Method for building automated co-verification platform on the basis of memory access driving

Abstract

The invention discloses a method for building an automated co-verification platform on the basis of memory access driving. The method comprises the following steps of: according to a data processing flow, constructing a programming language function model, and storing the relevant information of an access memory as the reference information of the programming language function model; monitoring the read-write signals of all memories in an RTL (Register Transfer Level) subsystem, calling a data comparison interface by a RTL verification module if the enabling of the read-write signals is detected, comparing the relevant information of a RTL operation memory with the reference information of the programming language function model, and proving that verification is qualified if all comparison results are consistent; and if any one comparison result is consistent, generating interruption, and finishing a whole verification flow. When the method is adopted, the RTL subsystem can be accurately and efficiently tested, and the method has the advantages of being convenient in debugging and comprehensive in verification.

Description

technical field [0001] The invention relates to chip verification technology, in particular to a method for building an automatic cooperative verification platform based on memory access drive. Background technique [0002] In order to verify the subsystems inside the chip, or even the functions of the whole chip, it is often necessary to support the collaborative verification environment, that is, to use the C language model to simulate the functions of the subsystems to verify the correctness of the functions of the subsystems. Because subsystems are usually very complex, the C language model not only needs to verify the final output of the subsystem, but also needs to verify the content between the various modules that build the subsystem. [0003] Common co-verification methods are generally based on module output-driven co-verification methods, such as figure 1 As shown, this method divides the system function into multiple module units. After the input stimulus, the C...

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Problems solved by technology

There is no direct output for this module, so the correctness of data written to memory cannot be verified

[0005] 2. It cannot be applied to the collaborative verification of associated functional modules

For example, function A and function B, there is no problem when testing them separately, but function A may change some state or store information in the RTL submodule, resulting in an error in function B when function A and function B are tested together

Although testing function A and function B together can solve the above problems, there is no guarantee that testing function A and function B together will not affect the testing of other functions

The above co-simulation method is not only very easy to miss test cases, but also causes the number of test cases to grow exponentially

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