Built-in self-testing circuit of memory suitable for various periodic testing algorithms

Abstract

The invention provides a built-in self-testing circuit of a memory suitable for various periodic testing algorithms. A composition module comprises a built-in self-testing control unit, a clock control signal generator, an address generator, a data generator, a data comparator, an optional delay unit and a plurality of control registers, wherein each control register comprises an address scanning register, an algorithm element register, an algorithm operation register, a data register and a delay register; the built-in self-testing control unit controls other modules to cooperatively work; the clock control signal generator, the address generator and the data generator generate a clock control signal, an address signal and a data signal required by the memory for operation respectively; and the data comparator judges the data reading correctness of the memory and feeds the result back to the built-in self-testing control unit. Various common periodic memory testing algorithms can be achieved by arranging the control registers; and testing and problem analysis work of the memory can be conveniently completed by a corresponding command and an operating state machine design.

Description

technical field [0001] The invention relates to the design field of memory design for test (DFT), more specifically, the invention relates to a memory built-in self-test circuit suitable for various periodic test algorithms. Background technique [0002] The testability design of various memories in SOC chips is a key design task. The MBIST (Memory Built-In Self Test) module that realizes this function is an important module of modern SOC chips, which is very important for reducing test costs. , Improving the ability to analyze memory failure issues plays a key role. For different memory types or different test requirements, MBIST will use different test algorithms. For the usual memory test process, commonly used test algorithms are: All0 / All1, CheckBoard / Invert CheckBoard, Diagonal, various March algorithms, read and write current test algorithms, etc. [0003] Usually, MBIST design is to determine several test algorithms according to the determined memory type, structur...

AI Technical Summary

Problems solved by technology

Its disadvantages are: the MBIST algorithm of each memory needs to be designed separately, the development cost is high and the cycle is long; the test algorithm of one MBIST is fixed, and other algorithms cannot be used according to actual needs, which is not conducive to the optimization consideration of test cost and debugging requirements

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