A speed hierarchical optimization structure and method for improving the output of high-performance integrated circuits

Abstract

The invention relates to a speed grading optimization structure and method capable of improving the yield of high-performance integrated circuits. The structure is embedded in an integrated circuit and is characterized in that an integrated circuit chip comprises N critical paths, i.e., critical path A, critical path B...critical path N, which jointly form a critical path set [A, B...N], the time delay of the N paths decides the speed grading of the integrated circuit. The adopted method comprises the following steps of: 1. selecting critical paths; 2. inserting an integrated circuit speed grading optimization structure; 3. testing an integrated circuit chip at a frequency boundary Fi; 4) obtaining an original speed grading result; 5. performing speed grading optimization; 6. testing again at the frequency boundary Fi; 7. re-dividing the speed grade of the integrated circuit chip; 8. deciding the speed grade and calculating a speed grading optimization rate; 9. marking the speed grade and working frequency of the integrated chip.

Description

Technical field [0001] The invention relates to an integrated circuit chip speed grading optimization structure and optimization method, more specifically, a speed grading optimization structure suitable for improving the output of high-performance integrated circuit chips during the speed grading process of integrated circuit chips and its performance Optimized method. Background technique [0002] An integrated circuit is a kind of miniature electronic device or component. It is through the semiconductor manufacturing processes of oxidation, photolithography, diffusion, epitaxy, and aluminum evaporation, the semiconductor, resistor, capacitor and other components required to form a circuit with a certain function and the connecting wires between them are all integrated into a small piece of silicon On-chip, then solder the electronic devices packaged in a tube case; all of the components have been structured as a whole, making the electronic components a big step towards minia...

AI Technical Summary

Problems solved by technology

For example, the working clock of the originally designed integrated circuit is 20ns, and the delay of the path with the longest delay in the chip is 19ns. However, due to the influence of process errors, for different batches of integrated circuits, the delay of this path may be 21ns. It may also be 15ns, so the working clock of the integrated circuit may be above 20ns, or below 20ns, which means that the maximum operating speed of different individuals of the same integrated circuit is inconsistent

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