All-digitally controlled phase-locked loop with low jitter and wide capturing frequency range

Abstract

The invention discloses an all-digitally controlled phase-locked loop with low jitter and a wide capturing frequency range. The phase-locked loop comprises a (timer digital converter) TDC module, a digital filter, a (digitally controlled oscillator) DCO module, a binary frequency divider and a variable-mode frequency divider, wherein the TDC module compares phases of an input reference clock and a feedback clock, and outputs a phase error signal; the digital filter converts the phase error signal into a set of control words, and the DCO module adjusts frequency and phase of an output clock according to the set of control words; the binary frequency divider reduces the frequency of the output clock to a half, and generates the feedback clock to TDC module for comparison after the variable-mode frequency divider implements frequency division according to a preset module value; circulation is implemented hereunder until the frequency of the reference clock is accordant with that of the feedback clock, and when the phase reaches a preset error, the all-digitally controlled phase-locked loop is locked. The TDC module reduced output jitter, the capturing frequency range of the phase-locked loop is broadened by the adjustment of the DCO module, and thus the problem that the existing all-digitally controlled phase-locked loop is relatively high in jitter value and relatively narrow in capturing frequency range is solved.

Description

technical field [0001] The invention relates to the technical field of phase-locked loops, in particular to an all-digital phase-locked loop with low jitter and wide capture frequency range. Background technique [0002] Phase-locked loop (Phase-Locked Loop, PLL) is an automatic control feedback system, which generates a clock signal with the same frequency and phase as the reference clock signal by comparing the frequency phase of the external reference clock signal and the feedback clock signal. In other words, the PLL is used to lock and track the frequency and phase of the reference clock signal. When the phase-locked loop is in the locked state, the frequency of the feedback clock is consistent with the frequency of the reference clock, and there is a slight error between the phase of the feedback clock and the phase of the reference clock. [0003] According to different design methods, phase-locked loops can be divided into analog phase-locked loops, digital phase-lo...

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Problems solved by technology

[0006] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a low jitter wide capture frequency range of the full digital phase-locked loop, to solve the existing full digital phase locked loop jitter value is higher, the capture frequency range is relatively narrow. narrow question

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