A Method for Obtaining Parasitic Capacitance Models Around the Gate of 3D MOS Devices

Abstract

The invention discloses a method for acquiring a gate fringe parasitic capacitance model of a three-dimensional MOS device. The method comprises the steps of 1: dividing gate fringe parasitic capacitance of the three-dimensional MOS device to obtain a basic capacitance structure model containing parallel plate capacitance and perpendicular plate capacitance; 2: approximately calculating unit capacitance of the basic capacitance structure model; 3: deducing a multi-media perpendicular plate capacitance model based on conformal mapping; and 4: extracting a correction factor of the multi-media perpendicular plate capacitance model, and correcting the multi-media perpendicular plate capacitance model according to the correction factor so as to obtain the gate fringe parasitic capacitance model of the three-dimensional MOS device. The model proposed in the method is incorporated into an actual situation of a multimedia material, so that the gate fringe parasitic capacitance of the three-dimensional MOS device can be accurately calculated; and according to the method, few fitting parameters are required and the applicability is wide.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, in particular to a method for obtaining an accurate model of parasitic capacitance around a gate of a three-dimensional MOS device. Background technique [0002] With the gradual reduction of the feature size of the semiconductor integrated circuit process to the nanometer field, the three-dimensional MOS device has gradually become the mainstream core device, and a complete set of models that accurately describe the working state and performance of the device is a major problem that needs to be solved and improved urgently. Among them, the parasitic capacitance around the Fin structure is difficult to accurately model because of its three-dimensional structure and filling with various materials. Therefore, the accurate model of the parasitic capacitance of the three-dimensional MOS device is a difficult point in the complete set of device models, and it is also a key link in analyzing the...

AI Technical Summary

Problems solved by technology

The first method can only calculate accurate discrete capacitance data of a specific structure according to fixed conditions, but the calculation speed is slow, and it is impossible to obtain an accurate and continuous capacitance model with physical meaning and universal applicability, nor can it provide designers with accurate capacitance data. Analysis reference

The problem with the second method is that it is difficult to obtain a cell structure capacitance model based on physical meaning and simple formula, especially in the case of multiple materials, it is difficult to establish a capacitance model

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