Memory controller and related control method

Abstract

The invention relates to a memory controller and a related control method. The memory controller comprises an address decoder and a protocol controller, wherein the address decoder is used for performing a decoding operation on a received signal to generate a plurality of instruction signals, and the instruction signals include an instruction signal which accesses a plurality of blocks in a memory; and the protocol controller is used for re-deciding an executive sequence of a plurality of the instruction signals according to enabled blocks and data pages in the memory at present to use a plurality of the instruction signals to access the memory.

Description

technical field [0001] The invention relates to memory, in particular to a dynamic random access memory controller and a related control method. Background technique [0002] In synchronous dynamic random access memory (Synchronous Dynamic Random-Access Memory, SDRAM), the data access (Read / Wrtie data) program includes the following actions: (1) If the corresponding block (Bank) is not set Data page (non-active page), you need to issue an active command (Active command) to open its access to the specific data page of the corresponding block, and then issue a read / write command (Read / Write command) to perform data reading Read / write action; (2) If the data page (active page) of the corresponding block has been set, then when corresponding to the same data page (page hit) of the block, the operation access can be directly performed; and when the corresponding When the data pages are different (page miss), you need to issue the precharge command (Precharge command) to close th...

AI Technical Summary

Problems solved by technology

However, through the finite state machine approach, there are usually limitations in the efficiency of system execution, which cannot increase the frequency of executing instructions, and will also delay the execution cycle, which will reduce the performance of memory access operations.

[0004] In order to improve the performance of SDRAM, generally speaking, by using optimization to determine the program flow, and changing the design of the hardware to pipeline (pipeline), the SDRAM instruction operation can be optimized, and then the bandwidth of the memory can be effectively improved, but its disadvantage is in the control It will increase its complexity and design difficulty, so the hardware design cost will also increase

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