A data processing apparatus and method for performing segmented operations

A technology for data processing equipment and operands, which is applied in electrical digital data processing, machine execution devices, program control design, etc., and can solve problems such as GPU difficulties.

Active Publication Date: 2016-09-21
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While GPUs are good at overlapping computations with memory accesses and thereby hiding latency, GPUs struggle when irregularities in data structures manifest themselves as computational load imbalances

Method used

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  • A data processing apparatus and method for performing segmented operations
  • A data processing apparatus and method for performing segmented operations
  • A data processing apparatus and method for performing segmented operations

Examples

Experimental program
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Embodiment Construction

[0060] figure 1 The execution of a compute descriptor operation is schematically shown according to one embodiment. Specifically, in one embodiment, assertion generation circuitry within the data processing device is configured to generate per-lane assertion information 15 in response to a compute descriptor instruction specifying an input vector operand 10 comprising a plurality of segment descriptors, the The per-lane assertion information 15 is then used by the vector processing circuitry of the data processing device to perform segmentation operations. In one embodiment, such as figure 1 As shown, the input vector register 10 contains a sequence of unsigned data values. In a specific embodiment, the input vector register 10 contains a series of 8 32-bit unsigned values. Each unsigned value in this embodiment indicates the end of a segment.

[0061] In this example, it is assumed that the vector processing circuitry provides 8 parallel processing lanes, and thus can per...

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Abstract

A data processing apparatus and method are provided for performing segmented operations. The data processing apparatus comprises a vector register store for storing vector operands, and vector processing circuitry providing N lanes of parallel processing, and arranged to perform a segmented operation on up to N data elements provided by a specified vector operand, each data element being allocated to one of the N lanes. The up to N data elements forms a plurality of segments, and performance of the segmented operation comprises performing a separate operation on the data elements of each segment, the separate operation involving interaction between the lanes containing the data elements of the associated segment. Predicate generation circuitry is responsive to a compute descriptor instruction specifying an input vector operand comprising a plurality of segment descriptors, to generate per lane predicate information used by the vector processing circuitry when performing the segmented operation to maintain a boundary between each of the plurality of segments. As a result, interaction between lanes containing data elements from different segments is prevented. This allows very effective utilisation of the lanes of parallel processing within the vector processing circuitry to be achieved.

Description

technical field [0001] The present invention relates to a data processing device and method for performing segmentation operations. Background technique [0002] One known technique to increase the performance of data processing devices is to provide circuitry that supports the operation of vector operations. Vector operations are performed on at least one vector operand, where each vector operand includes a plurality of data elements. Performing a vector operation involves repeatedly applying an operation across multiple data elements within a vector operand. [0003] In a typical data processing system that supports the implementation of vector operations, a vector register file will be provided for storing vector operands. Thus, by way of example, each vector register within a vector register file may store a vector operand comprising a plurality of data elements. [0004] It is known that in some embodiments, a vector processing circuit (commonly referred to as a SIMD...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
CPCG06F9/30014G06F9/30036G06F9/30072G06F9/30076G06F9/3887G06F9/3891G06F9/3001G06F9/30098
Inventor 姆布·埃约勒-莫诺诺阿拉斯塔尔·大卫·瑞德马蒂亚斯·洛塔尔·博彻贾科莫·加布雷利
Owner ARM LTD
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