A controllable dynamic multithreading method and processor

Abstract

The invention discloses a controllable dynamic multi-thread method and a processor. The method comprises the following steps: newly increasing a mark in an instruction structure of a processor adopting a pipeline structure, wherein the mark comprises two parts of information: a thread of a corresponding instruction of the mark, and priority level information of the corresponding instruction of the mark; controlling the corresponding instruction by the processor according to the mark; and transmitting and executing instruction according to the thread and the priority level information in the mark. The processor at least comprises an instruction system containing the mark, a program executing control unit (Branch) capable of identifying and tracking the mark, an instruction decoding circuit capable of identifying and decoding the mark, an arithmetic operation unit capable of identifying and decoding the mark and a corresponding memory unit. According to the controllable dynamic multi-thread method and the processor, all operation hardware resources of one processor can be dynamically dispatched, so that the operation capability of the processor is improved, and more complicated hardware does not need to be increased.

Description

technical field [0001] The present invention relates to the field of processors, in particular to a controllable dynamic multi-threading method (Dynamic Multi-threading) and a processor. Background technique [0002] In order to improve the computing power of the processor, many parallel processing technologies have been developed, such as super-scalar (Super-scalar), pipeline (Pipeline), very long and wide instruction (VLIW), single instruction multiple execution (SIMD), and so on. However, since the instruction processing of a software program is executed sequentially, the dependencies of instructions and data in the execution process cause the processor to be in a waiting state often, thus limiting the efficiency of these parallel processing technologies. [0003] In order to overcome the dependency in instruction execution, some technologies to improve instruction emission efficiency, such as out-of-order code (Out-of-Order), control program prediction (Branch Prediction...

AI Technical Summary

Problems solved by technology

[0023] From the above analysis, it can be seen that the hardware complexity of the processor using opportunistic multi-programming technology is much higher than that of token-driven multi-threading technology, and in order to enable each thread to read instructions at each clock cycle, the instruction memory The clock frequency must be the same as the main oscillator frequency of the processor, so the power consumption of the processor will increase significantly

Therefore, opportunistic multi-threading technology is not suitable for low-power embedded processor design

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