A routing structure about dram clock tree

Abstract

The invention relates to a DRAM clock tree routing structure. The DRAM clock tree routing structure comprises a substrate, a clock tree layer and an isolation unit between the substrate and the clock tree layer, wherein the isolation unit comprises a stray capacitor C1, a stray capacitor C2 and at least one isolation layer between the stray capacitor C1 and the stray capacitor C2; the other end of the stray capacitor C1 is connected with a clock signal wire; the other end of the stray capacitor C2 is connected with the substrate. In order to solve the technical problem that the conventional DRAM clock tree layout introduces the noise of the substrate into clock signals, the routing structure is adopted; the routing structure can be used for shielding and reducing the crosstalk from the noise of the substrate to the clock tree and keeping the consistency of the clock tree routing environment.

Description

technical field [0001] The invention relates to a DRAM clock tree wiring structure. Background technique [0002] The existing DRAM clock tree layout is only isolated on the side of the same layer, that is, which wiring layer of the clock layer is wired, and the isolation line is also wired on both sides of the clock tree at the same level for isolation, specifically as follows figure 1 shown. figure 2 It is a cross-sectional view of the DRAM clock tree layout, which describes the partial tree structure of the clock tree, isolation lines, and the relationship with the substrate. Substrate-to-clock tree noise is passed through the parasitic capacitance C total coupled to the clock signal. There is no shielding for this part of the noise, but this part of the noise will have a serious impact on key signals and high-frequency signals. [0003] There is following shortcoming in existing this layout: [0004] 1. The environment around the clock tree routing is different, wh...

AI Technical Summary

Problems solved by technology

[0006] In order to solve the technical problem that the existing DRAM clock tree layout will introduce substrate noise into the clock signal, the present invention provides a DRAM clock tree routing structure

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