Function verification method and platform for DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller

A function verification and controller technology, which is applied in the direction of instruments, static memory, etc., can solve the problems of limiting DDR3 SDRAM read and write performance, and achieve the effect of convenient maintenance and upgrading, reducing the chance of omissions and errors, and facilitating maintenance and upgrading

Active Publication Date: 2016-06-08
SHENZHEN PANGO MICROSYST CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These delay requirements objectively limit the read and write performance of DDR3SDRAM

Method used

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  • Function verification method and platform for DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller
  • Function verification method and platform for DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller
  • Function verification method and platform for DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller

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Experimental program
Comparison scheme
Effect test

test Embodiment 11

[0033] Test case 11, used to detect the correctness of user read and write operations, specific user interface timing or signals;

[0034] The port monitoring module 12 designed with hierarchical and object-oriented technology is used to detect the correctness of the DDR3 SDRAM port signal.

[0035] In some embodiments, the port monitoring module 12 in the above-mentioned embodiments is used to package the signal of the DDR3SDRAM port as a command service in units of commands, monitor and analyze the command service according to the state table, and determine the correctness of the DDR3SDRAM port signal according to the analysis result. sex.

[0036] In some embodiments, the port monitoring module 12 in the above embodiments is also used to set the main content, logical structure, member variables and member methods of the command service.

[0037] In some embodiments, the logic structure in the above embodiments is a tree logic structure including commands, non-MRS commands,...

no. 2 example

[0041] figure 2 The flow chart of the function verification method provided by the second embodiment of the present invention is composed of figure 2 It can be seen that, in the present embodiment, the functional verification method for the DDR3 SDRAM controller provided by the present invention comprises the following steps:

[0042] S201: The test case detects the correctness of user read and write operations, specific user interface timing or signals;

[0043] S202: A port monitoring module designed with hierarchical and object-oriented technology is used to detect the correctness of the DDR3 SDRAM port signal.

[0044] In some embodiments, the port monitoring module in the above-mentioned embodiments detects the correctness of the DDR3SDRAM port timing including: encapsulating the signal of the DDR3SDRAM port as a command service in units of commands, monitoring and analyzing the command service according to the state table, and according to the analysis result Determi...

no. 3 example

[0050] The present invention will be further explained in combination with specific application scenarios.

[0051] The agreement stipulates many timing constraints of DDR3SDRAM in the work. These timings are complex and easy to be overlooked during verification. Therefore, how to effectively find an architecture that can effectively organize these constraints in time and space is an important issue. . The role of the verification platform in chip verification determines that the code of the verification platform should be easy to maintain and robust; in addition, considering the future development of the DDR series, it also needs to have good adaptability to facilitate future possible new additions. Function, only need to add and modify a small amount of code to upgrade the verification platform.

[0052] Based on the above-mentioned technical status, this embodiment provides a test platform using SystemVerilog language programming. The overall structure of the test platform...

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Abstract

The invention provides a function verification method and platform for a DDR3 SDRAM (double data rate 3 synchronous dynamic random access memory) controller. The function verification method comprises steps as follows: adopting a test case to detect correctness of user read-write operation, specific user interface timing sequences or signals; adopting a port monitoring module designed with layering and object oriented technologies to detect correctness of DDR3 SDRAM port signals. According to the invention, the design of the port monitoring module adopts layering and object oriented design methods, so that various timing sequence constraints at a DDR3 SDRAM port are effectively organized in the aspects of time and space, the probability of omission is low, and maintenance and upgrading are facilitated.

Description

technical field [0001] The invention relates to the verification field of DDR3 SDRAM controllers, in particular to a function verification method and platform for DDR3 SDRAM controllers. Background technique [0002] DDR3SDRAM is the third generation of high-performance DDRSDRAM (double data rate synchronous dynamic random access memory, double data rate synchronous dynamic random access memory) proposed to adapt to the development of computer technology. The advantages of data capacity and lower power supply voltage make it more suitable for the requirements of the new generation of storage technology. In addition, DDR3SDRAM also adopts new technologies such as ODT (on-line debugging technique, online debugging technology) to further ensure the signal integrity of data during high-speed transmission. [0003] The DDR3SDRAM protocol stipulates that data transmission is completed by issuing read and write commands and corresponding data to DDR3SDRAM in the normal working mod...

Claims

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Application Information

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IPC IPC(8): G11C29/56
CPCG11C29/56
Inventor 蒋德
Owner SHENZHEN PANGO MICROSYST CO LTD
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