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Parallel processing method for reconfigurable processor with multilayer heterogeneous structure

A technology of heterogeneous structure and parallel processing, applied in the direction of machine execution device, concurrent instruction execution, etc., can solve the problems of complex parallel language expansion and so on

Active Publication Date: 2016-02-03
SHANGHAI JIAO TONG UNIV
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  • Abstract
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  • Claims
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Problems solved by technology

However, the reconfigurable processors targeted by these compilation processes all have a two-layer heterogeneous structure, and the extension of parallel languages ​​is relatively complicated.

Method used

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  • Parallel processing method for reconfigurable processor with multilayer heterogeneous structure
  • Parallel processing method for reconfigurable processor with multilayer heterogeneous structure
  • Parallel processing method for reconfigurable processor with multilayer heterogeneous structure

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Embodiment Construction

[0026] The following describes the implementation of the present invention through specific specific examples in conjunction with the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the spirit of the present invention.

[0027] figure 1 It is a schematic diagram of the architecture of a reconfigurable processor with a multi-level heterogeneous structure applied in the present invention. Such as figure 1 As shown, the reconfigurable processor for multi-level heterogeneous structure applied in the present invention includes: an ARM11 core 10 (main controller), a main memory DDR20 and multi...

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Abstract

The invention discloses a parallel processing method for a reconfigurable processor with a multilayer heterogeneous structure. The method comprises: step 1, obtaining code intermediate representation (IR) of class assembly, and extracting an instruction; step 2, analyzing the extracted instruction, and constructing an instruction dependency graph according to data flow; step 3, calculating an iterative interval, wherein the iterative interval refers to a clock cycle of an interval of repeatedly performing two same instructions by a single processing element (PE); step 4, constructing CONFIGIR configuration information, wherein the CONFIGIR configuration information contains a reconfigurable PE array number of an execution configuration package, the length of the configuration package and an operation instruction in each piece of configuration information; step 5, obtaining access information; and step 6, performing binary mapping on the CONFIGIR configuration information. With the method, a three-layer heterogeneous reconfigurable processor architecture oriented back end processing scheme is realized.

Description

Technical field [0001] The invention relates to the field of reconfigurable computing, in particular to a parallel processing method for a reconfigurable processor with a multi-level heterogeneous structure. Background technique [0002] The reconfigurable processor is an important product to meet people's needs for computing speed and computing versatility in the information age. It combines the advantages of general-purpose processors and application-specific integrated circuits. A typical coarse-grained reconfigurable processor is composed of a main controller, a main memory DDR and a reconfigurable processing unit (RPU), and the data transmission between each part is realized through a bus. The main controller is used to run the operating system and is responsible for the scheduling of the entire system resources. When a computing task runs on a reconfigurable processor, the compiler divides the task code into software and hardware. Software and hardware division refers to ...

Claims

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Application Information

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IPC IPC(8): G06F9/38
Inventor 刘毅超赵仲元绳伟光何卫锋
Owner SHANGHAI JIAO TONG UNIV
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