Configuration circuit capable of completing FPGA re-configuration through user input and output port

Abstract

The invention provides a configuration circuit capable of completing FPGA re-configuration through user input and output ports. Through adding a user configuration interface circuit in a conventional configuration circuit structure, user input and output ports (user IOB) are connected with the configuration circuit, so as to provide conditions for the user input and output ports to access the configuration circuit and completing dynamic re-configuration. A bus interface circuit in the configuration circuit is improved, so the circuit is compatible to three operating modes of parallel configuration of the user input and output ports, parallel configuration of system input and output ports, and serial configuration. The configuration circuit prevents dependence on fixed system input and output ports, and FPGA devices can still change internal functions thereof after being built in a user system, so as to realize intra-system reconfigurability, and flexibility and reliability of a FPGA chip are improved.

Description

technical field [0001] The invention relates to an FPGA configuration circuit, in particular to a configuration circuit capable of completing dynamic reconfiguration of the FPGA through user input and output ports. Background technique [0002] figure 1 It is a block diagram of FPGA, the input and output ports (IOB) are located around the chip, the configurable logic module (CLB) is arranged in an array internally, and the block memory (BRAM) is interspersed in the configurable logic module (CLB), including configuration logic and configuration interface. figure 1 Only a small number of Input Output Blocks (IOBs) and Configurable Logic Blocks (CLBs) and Block Memory (BRAM) are shown for illustration purposes only. FPGAs also contain other components: a programmable interconnect that connects blocks throughout the chip and configuration memory arrays (CSRAM), which are in the figure 1 There are no specific illustrations. The SRAM configuration bits in the configuration me...

AI Technical Summary

Problems solved by technology

However, the configuration circuit in the traditional FPGA chip can only receive configuration data from a few fixed system input and output ports. The output port performs massive read and write operations on the FPGA, which is not conducive to the full utilization of resources and affects the reliability of the device

Images