Power and area optimization method of incomplete certain Reed-Muller circuit based on NSGA-II

Abstract

The invention provides a power and area optimization method of an incomplete certain Reed-Muller circuit based on NSGA-II. The method comprises the steps of (1) converting an incomplete certain Boolean logic function into a zero polarity incomplete certain RM expression, (2) encoding the binary number of don't care term option of the incomplete certain Boolean logic function as a chromosome, (3) establishing a power area estimation model, (4) establishing a power area target function, (5) establishing fitness functions related to a power and an area, (6) determining a constraint, (7) initializing parameters, (8) generating an initial population and performing non-dominated sorting, (9) performing selection crossover and mutation and generating a son generation population, (10) combining father and son generation populations and performing non-dominated sorting, (11) calculating an individual crowding degree in a non-dominated layer and forming new father and son generation populations, (12) performing selection crossover and mutation on the new father and son generation populations and generating a new son generation population, (13) returning to the step (10) if current evolution generation number is smaller than or equal to a maximum evolution generation number, otherwise, outputting an optimal solution set, and (14) selecting an optimal don't care term option from the optimal solution set and obtaining a corresponding complete certain RM expression.

Description

technical field [0001] The invention relates to an optimization method for power consumption and area of ​​an incompletely determined Reed-Muller circuit, in particular to a method for optimizing power consumption and area of ​​an incompletely determined Reed-Muller circuit based on NSGA-II. The invention belongs to the technical field of logic functions and logic circuits. Background technique [0002] The logic function can be realized not only by Boolean logic based on AND / OR / NOT operation, but also by Reed-Muller (RM) logic based on AND / XOR or XNOR / OR operation. For some circuits, such as arithmetic circuits, parity check circuits, and communication circuits, where XOR operations are more frequent, compared with Boolean logic implementations, RM logic implementations have greater advantages in terms of power consumption, area, and speed. And because the change of a certain input of the XOR gate will directly cause the change of its output, the RM logic circuit also has ...

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Problems solved by technology

[0009] (2) The research on the optimization of RM logic circuits considering irrelevant items mainly focuses on the polarity conversion of RM expressions including irrelevant items and the simplification of logic function expressions. Few studies use irrelevant items to compare the power consumption of RM logic circuits Simultaneous optimization of area

However, because the traditional weighted summation method has various defects such as being unable to solve the non-convex Pareto front, the distribution of the solution is not uniform enough, it is necessary to manually set multiple sets of different weights and perform multiple operations to obtain the Pareto optimal solution set, etc. The RM logic circuit power consumption and area optimization method of the summation method is not effective, and has certain limitations in practical applications

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