A construction method of high-efficiency x-structure obstacle-avoiding router for multi-layer chips
An obstacle-avoiding router and multi-layer chip technology, which is applied in instruments, special data processing applications, electrical digital data processing, etc., can solve problems such as difficult problems, and achieve the effects of compact logic, compressed line length, and increased total length of shared paths
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[0019] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.
[0020] A method for constructing an efficient X-structure obstacle-avoiding router for multilayer chips, comprising the following steps:
[0021] Step S1: According to a given set of pin coordinate positions, a 3D-OFMST connecting all pins is generated based on a fast multi-slice MST construction strategy, and the 3D-OFMST is the basic structure of the final ML-OAXSMT;
[0022] Step S2: The XRP information of all edges in 3D-OFMST is calculated, and these information are stored in two records to generate two lookup tables, which can provide information support for the subsequent operation of the router;
[0023] Step S3: Based on the quick table lookup, generate an ML-XST by converting each edge of the 3D-OFMST into an XRP, and convert the ML-XST into an ML-OAXST;
[0024] Step S4: Further optimize ML-OAXST from both global and local perspecti...
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