A Hybrid 3D Network-on-Chip

A network-on-chip, hybrid technology, applied in the direction of instruments, computers, calculations, etc., can solve the problems of increased communication power consumption and system transmission delay, and achieve the goal of increasing internal bandwidth, shortening the global interconnection length, and increasing interconnection Effect

Active Publication Date: 2018-07-13
INSPUR BEIJING ELECTRONICS INFORMATION IND
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The increase of the connection length directly brings about the increase of the system transmission delay, which limits the increase of the data transmission frequency. At the same time, due to the increase of the global connection length and the number of data forwarding times, the communication power consumption of the system will also increase.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A Hybrid 3D Network-on-Chip
  • A Hybrid 3D Network-on-Chip
  • A Hybrid 3D Network-on-Chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0031] The embodiment of the invention discloses a hybrid three-dimensional on-chip network to reduce the length of the connection and the diameter of the network, reduce system transmission delay, and reduce communication power consumption.

[0032] see figure 1 , a hybrid three-dimensional network on chip provided by an embodiment of the present invention, including:

[0033] A plurality of horizontal sublayers stacked in the vertical direction; wherein, the hor...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The embodiment of the present invention discloses a hybrid three-dimensional network on chip, including: a plurality of horizontal sub-layers stacked in the vertical direction; wherein, the horizontal routing units in each horizontal sub-layer maintain the same topology; connecting the The vertical buses of the horizontal routing units located on the same vertical line in multiple horizontal sub-layers; wherein, the number of the vertical buses corresponds to the number of horizontal routing units in each horizontal sub-layer; control the vertical The vertical bus controller of the bus occupancy, by stacking multiple horizontal sub-layers in the vertical direction, forms a three-dimensional on-chip network, increases the interconnection in the vertical direction, shortens the global interconnection length inside the chip, and improves the internal bandwidth of the chip , reducing the delay and power consumption of data transmission.

Description

technical field [0001] The present invention relates to the technical field of on-chip network, and more specifically, relates to a hybrid three-dimensional on-chip network. Background technique [0002] Network-on-Chip (NoC) interconnection structure has become the development trend of chip architecture design, and it is one of the effective solutions for future on-chip IP core interconnection. The multi-core processor system-on-a-chip based on the NoC architecture can realize the separation of computing and communication. The computing subsystem composed of IP cores can independently complete computing tasks, and the communication subsystem composed of NoC is responsible for high-speed data exchange between IP cores. As the integrated circuit process enters the 14nm process era, the design scale of NoC continues to expand. Since all resource nodes are laid out on the plane, and the layout and wiring are carried out on the two-dimensional plane, the interconnection lines be...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/173
Inventor 张闯
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap