Time-interleaved pipeline analog-to-digital converter

Abstract

The invention discloses a time-interleaved pipeline analog-to-digital converter. An ADC structure is provided with asub circuit with 4 stages of pipelines or above 4 stages of pipelines, wherein pipeline Stage 1 uses the structure of a traditional pipeline analog-to-digital converter and comprises Sub-adc, Sub-dac and a margin amplifier circuit. The pipeline Stage 2 and the pipeline Stage 3 further comprise signal paths chA and signal paths chB besides the sub-cirsuit of the pipeline Stage 1, and pipeline Backend comprises the sub-circuit of one-stage or multistage similar pipeline Stage 2, pipeline Stage 3 and a one-stage FLASH circuit. Compared with the traditional pipeline analog-to-digital converter, the time-interleaved pipeline analog-to-digital converter of the invention reduces unit bandwidth gain product requirement of an operational amplifier by increasing the establishing time of all stages of margin amplifiers under a fixed sampling rate , thereby reducing the power consumption of each stage of the operational amplifier.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to the circuit structure of an analog-to-digital converter. Background technique [0002] In the past few decades, integrated circuit technology has been developed rapidly. Especially the electronic system headed by communication is constantly developing towards the direction of high speed, high performance, high integration and low cost. This puts forward higher requirements for each module in the system. such as an analog-to-digital converter. While the system requires improving the sampling rate and quantization accuracy of the analog-to-digital converter, it also hopes to improve the conversion efficiency of the analog-to-digital converter and reduce its power consumption. [0003] As the sampling rate increases, the settling time of the headroom amplifier of the pipelined ADC becomes shorter. For the traditional pipeline circuit structure, the band...

AI Technical Summary

Problems solved by technology

However, under the premise of the same process conditions, the bandwidth of high-speed operational amplifiers cannot be effectively improved by increasing power consumption.

Moreover, while increasing the bandwidth of the op amp, it reduces its DC gain and reduces the effective settling accuracy of the headroom amplifier

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