Vertically-stacked strain Si/SiGe heterojunction CMOS device structure and preparation method thereof

Abstract

The invention discloses a vertically-stacked strain Si / SiGe heterojunction CMOS device structure and a preparation method thereof. The device comprises a silicon substrate, a relaxation SiGe buffer layer, a relaxation Si0.7Ge0.3 virtual substrate, an n<+> delta doping layer, a relaxation Si0.7Ge0.3 interval layer, a strain Si trench, a relaxation Si0.7Ge0.3 intermediate layer, a strain Si0.5Ge0.5 trench, a relaxation Si0.7Ge0.3 cap layer and a Si cap layer from the bottom up in sequence. An n-MOSFET trench adopts a tensile strain Si material, a p-MOSFET trench adopts a compression strain SiGe material, and the n-MOSFET and the p-MOSFET adopt a vertically-stacked structure, and share one polycrystalline SiGe gate electrode, so that electron and hole migration rates are improved greatly, speed and integration level of chips are improved, and new technological approaches are provided for high speed and high frequency development of the Si device and an integrated circuit.

Description

technical field [0001] The invention relates to the technical field of semiconductor device preparation, in particular to a vertically stacked strained Si / SiGe heterojunction CMOS device structure and a preparation method thereof. Background technique [0002] Semiconductor integrated circuits are the foundation of the electronics industry, and people's huge demand for the electronics industry has prompted the rapid development of this field. In the past few decades, the rapid development of the electronics industry has had a huge impact on social development and national economy. At present, the electronics industry has become the largest industry in the world, occupying a large share in the global market, and its output value has exceeded 1 trillion US dollars. [0003] Si CMOS integrated circuits have the advantages of low power consumption, high integration, low noise and high reliability, and occupy a dominant position in the semiconductor integrated circuit industry. ...

AI Technical Summary

Problems solved by technology

With the continuous improvement of integrated circuit integration and the continuous reduction of feature size, a series of problems in materials, device physics, device structure and process technology have emerged, especially due to the hole mobility ratio of bulk Si material to electron mobility. Low, the performance of Si CMOS circuits is largely restricted by p-MOSFETs, which limits the further improvement of device performance

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