Frequency domain implementation method of high-speed high-order FIR filter used for FPGA

Abstract

The invention discloses a frequency domain implementation method of a high-speed high-order FIR filter used for FPGA. When convolution operation is processed by utilization of a frequency domain, the problem that data cannot be processed in real time caused by zero filing time consumption is solved, an original conventional scheme of processing a sequence by utilization of one FFT IP is changed to a scheme of operating inputted data by utilization of two FFT IPs. Two FFTs output sectional convolution data respectively, and the difference of the later convolution and the previous convolution is just N clocks. Because the length of the sectional convolution is 2N, the previous N data and the previous sectional convolution are added, and the later N data and the later sectional convolution are added. Thus superfluous time-delay is not needed during overlap addition, a convolution result can be obtained, and therefore signal in-real processing is achieved. The provided frequency domain implementation method can lower FPGA resource consumption, can eliminate zero filling delay phenomena in the prior art, raises the processing speed, and can achieve real-time processing.

Description

technical field [0001] The invention relates to the technical field of discrete signal processing, in particular to a frequency-domain implementation method of a high-speed high-order FIR filter for FPGA. Background technique [0002] In digital signal processing system, FIR (Finite Impulse Response) filter is the most basic unit. Due to its strict linear phase-frequency characteristics and stable system, FIR has become the main means of data processing in many fields. With the development of electronic technology, the signal sampling frequency is constantly increasing. Under high-speed sampling, the FIR filter based on the multiplier structure and the FIR filter based on the distributed algorithm can perform fast pipeline real-time processing in the FPGA, but like pulse The compression technology is similar to the FIR filter, and its order is tens of thousands, which consumes too much FPGA resources. [0003] The Fast Fourier Transform (FFT) is a method that can implement...

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Problems solved by technology

[0016] In order to solve the above problems, the object of the present invention is to provide a frequency-domain implementation method of a high-speed high-order FIR filter for FPGA, and improve the existing FFT method to solve the problem of reducing FPGA resource consumption and improving processing speed. The problem is: on the one hand, reduce the consumption of FPGA resources in high-order high-speed situations, and on the other hand, increase the processing speed to achieve real-time processing

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