Asynchronous decoder and method for bmc signal

A decoder and signal technology, which is applied in the field of asynchronous decoders, can solve problems such as poor performance and received data errors, and achieve the effects of fast self-adaptation, accurate decoding, and improved performance of received data

Active Publication Date: 2018-02-13
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The performance of the existing asynchronous decoder of the BMC signal is not good when the received signal has glitches, and it is easy to cause errors in the received data

Method used

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  • Asynchronous decoder and method for bmc signal

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Embodiment Construction

[0022] combine figure 2 The realization principle of the asynchronous decoder of the BMC signal as shown is as follows:

[0023] A clock with a frequency much higher than the bit rate of the BMC signal is used as the sampling clock, that is, the clock signal clk, and a level counter is used to record the number of clock signals counted in the low level or high level of the BMC signal being received. At the reset point of the level counter, the level counter is cleared to 0 and then counted.

[0024] A register is used to record the number of sampling points of half a bit width of the BMC signal (hereinafter referred to as the number of half-bit sampling points). Afterwards, at the decision point of each data, compare the value of the level counter with the number of half-bit samples, and if the value of the level counter is between 1.5 times and 2.5 times the number of half-bit samples, it is received If the value of the level counter is between 0.75 times and 1.5 times the...

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PUM

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Abstract

The invention discloses an asynchronous decoder for BMC signals, comprising: a deburring circuit, a phase jump detection circuit, a level counter, a register, an adaptive logic circuit, and a decision logic circuit. The phase jump detection circuit detects the edge of the phase change of the BMC signal, and uses the edge of the phase change as the decision point of the data, the reset point of the level counter and the update point of the number of half-bit samples. The level counter is used to record the number of samples of each level. At the judgment point of the data, it is judged whether the received one is 0 or 1 by comparing the size relationship between the level counter and the number of half-bit samples. The number is obtained by an adaptive logic circuit. The invention also discloses an asynchronous decoding method of the BMC signal. The invention can improve the receiving performance of the asynchronous decoder of the BMC signal and avoid receiving data errors.

Description

technical field [0001] The invention relates to an asynchronous decoder for BMC (Biphase Mark Coding) signals. The invention also relates to an asynchronous decoding method of the BMC signal. Background technique [0002] BMC signal encoding waveform such as figure 1 As shown, it belongs to a phase modulation coding method, which is a coding method that mixes clock and data for transmission; its principle is to use a clock frequency twice the transmission bit rate as a reference, and split the original bit data into Two parts, when the data is 1, the potential is changed once in the middle of the bit (1->0 or 0->1) to become 10 or 01, when the data is 0, the potential is not changed, and it becomes 11 or 00. At the same time, the level at the beginning of each bit is different from the level at the end of the previous bit, so that the receiving end can judge the boundary of each bit. The use of BMC encoding allows the transmitting end and the receiving end to transmit ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/00
Inventor 汤晓岚
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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