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Master-slave synchronous serial communication bus based on differential signal and its realization method

A technology of synchronous serial and communication bus, which is applied in the field of master-slave synchronous serial communication bus, which can solve the problems of inability to guarantee real-time transmission of large quantities of data and low transmission rate of master-slave synchronous serial communication, so as to improve distance and anti-interference ability, the effect of eliminating delay

Active Publication Date: 2017-06-20
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to solve the problem that the existing master-slave synchronous serial communication has a low transmission rate, cannot guarantee the real-time transmission of large batches of data, and the error detection can only complete single-byte verification, and provides a master-slave based on differential signals. Slave synchronous serial communication bus and its realization method

Method used

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  • Master-slave synchronous serial communication bus based on differential signal and its realization method
  • Master-slave synchronous serial communication bus based on differential signal and its realization method
  • Master-slave synchronous serial communication bus based on differential signal and its realization method

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specific Embodiment approach 1

[0026] Specific implementation mode one: the following combination figure 1 Describe this embodiment, the master-slave synchronous serial communication device based on differential signals in this embodiment, the communication device includes a master controller 1, a master isolation differential module 2, n slave isolation differential modules 3 and n slave controllers 4, n is a positive integer, the master controller 1 includes a master sending module M_TX and a master receiving module M_RX, and each slave controller 4 includes a slave sending module S_TX and a slave receiving module S_RX;

[0027] The main transmitting module M_TX and the main isolated differential module 2 are connected through the enable signal line M_TXD_EN, the clock signal line M_TXD_CLK and the data signal line M_TXD, and the main receiving module M_RX and the main isolated differential module 2 are connected through the clock signal line M_RXD_CLK and the data signal line M_RXD connection, the master...

specific Embodiment approach 2

[0028] Specific implementation mode two: the following combination figure 2 This embodiment is described. This embodiment will further explain Embodiment 1. The n slave isolation differential modules 3 have the same structure, and all include a digital isolation module 3-1, a DC / DC power isolation module 3-2, and an LDO voltage regulator module. 3-3. Differential module I3-4, differential module II3-5, current noise suppressor I3-6, current noise suppressor II3-7, bidirectional transient voltage control module I3-8, bidirectional transient voltage control module II3- 9. Two impedance matching resistors RI and RII;

[0029] The digital isolation module 3-1 and the slave transmitting module S_TX of the slave controller 4 are connected through the enable signal line S_TXD_EN, the clock signal line S_TXD_CLK and the data signal line S_TXD, and the digital isolation module 3-1 and the slave receiving module of the slave controller 4 S_RX is connected to the data signal line S_RXD...

specific Embodiment approach 3

[0035] Specific implementation mode three: the following combination Figure 3-Figure 6 Describe this embodiment, the implementation method of the master-slave synchronous serial communication device based on differential signals described in this embodiment, the specific process of this implementation method is:

[0036] The main controller 1 periodically reads the valid data in the dual-port memory RAM of the main receiving module M_RX, then inverts the sending end flag and assigns it to the sending start flag, and starts the main sending module M_TX;

[0037] The main controller 1 configures the time register group, the quantity register group, the reset identification register, the data packet start identification register, the address register group and the sending start identification bit in the main transmission module M_TX through the address bus and the data bus according to the system clock, and will The data packet to be sent is written into the dual-port memory RAM...

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Abstract

The invention provides a master-slave synchronous serial communication bus based on a differential signal and a realization method of the master-slave synchronous serial communication bus, relates to a master-slave synchronous serial communication bus, and aims at solving the problems that the existing master-slave synchronous serial communication is low in transmission speed, the real-time transmission of massive data cannot be guaranteed, and only the single byte check can be realized through code error detection. A master-slave synchronous serial communication bus based on the differential signal comprises a master controller, a master isolation difference module, n slave isolation difference modules and n slave controllers; the master controller comprises a master transmitting module and a master receiving module; each of the slave controllers comprises a slave transmitting module and a slave receiving module; the slave isolation difference modules are same in structure; each of the slave isolation difference modules comprises a digital isolation module, a DC / DC (Direct Current / Direct Current) power isolation module, an LDO (Low Dropout Regulator) voltage regulator module, two difference modules, two current noise suppressors, two two-way transient voltage control modules and two impedance matching resistors. The master-slave synchronous serial communication bus and the realization method of the master-slave synchronous serial communication bus are mainly used for master-slave synchronous serial communication.

Description

technical field [0001] The invention relates to a master-slave synchronous serial communication bus. Background technique [0002] The current master-slave synchronous serial communication mode means that all slave nodes in the digital network use the clock of the master node as a reference, and all nodes either receive the timing reference sent by the master node from the direct digital link, or receive the timing reference from the master node through the intermediate The timing reference sent by the master node is received on the digital link after the node forwards, so that the clock of the slave node is subordinate to the clock of the master node, such as SPI serial communication. Due to the influence of communication line delay, this type of communication method generally has a low transmission rate, and thus cannot guarantee real-time transmission of large batches of data. In terms of bit error detection, this type of communication method often uses a parity check me...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/42
CPCG06F13/4295
Inventor 张元飞金明河刘宏
Owner HARBIN INST OF TECH
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