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Method for acquiring the resistance of water-level bonding structure and semiconductor structure thereof

A bonding structure and wafer bonding technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve problems such as inaccurate bonding structure resistance

Active Publication Date: 2015-03-25
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In the resistance measurement circuit of the existing bonding structure, the measurement is performed by forming a series structure between the pads, the metal interconnection wires, and the conductive plugs connecting the two on the respective wafers. Since the pads, the conductive plugs, The resistance of the metal interconnection is generally separated from the total test results by empirical values, and the resistance of the bonding structure is much smaller than the resistance of the above three, so the resistance of the bonding structure obtained by the above method is not accurate

Method used

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  • Method for acquiring the resistance of water-level bonding structure and semiconductor structure thereof
  • Method for acquiring the resistance of water-level bonding structure and semiconductor structure thereof
  • Method for acquiring the resistance of water-level bonding structure and semiconductor structure thereof

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Embodiment 1

[0094] In this embodiment, the number of the first pads on the first wafer and the number of the second pads on the second wafer are two respectively to introduce the method of obtaining the resistance of the wafer-level bonding structure provided by the present invention. Semiconductor structures and methods thereof.

[0095] First refer to figure 1 The schematic cross-sectional structure of the first wafer is shown. The surface of the first wafer 10 has two first bonding pads 11 , which are bonding pads 111 and 112 respectively, and two adjacent first bonding pads 111 and 112 are electrically connected. In addition, the first wafer 10 also has first openings 121 , 122 for exposing the two first pads 111 , 112 respectively.

[0096] In this embodiment, the first pads 111, 112 are formed on the front surface 10a (the functional surface, that is, the surface where the active devices are located) of the wafer 10, and the electrical connections between the first pads 111, 112 a...

Embodiment 2

[0109] In the second embodiment, the number of the first pads on the first wafer and the number of the second pads on the second wafer are two respectively to introduce the wafer-level bonding structure provided by the present invention. Resistive semiconductor structures and methods thereof. For semiconductor structures, refer to Figure 5 The schematic cross-sectional structure diagram of the first wafer 10 shown, and Figure 6 The schematic diagram of the cross-sectional structure of the second wafer 20 shown is different from the first openings 121 and 122 on the first wafer 10 in the first embodiment for exposing the two first pads 111 and 112 respectively. The second wafer 20 has second openings 221 , 222 for exposing two second pads 211 , 212 respectively. In other words, if Figure 7 As shown, the measurement points A and B of the resistance of the structure after the bonding of the first wafer 10 and the second wafer 20 are located on the second wafer 20 .

[0110...

Embodiment 3

[0113] In this embodiment, the number of the first pads on the first wafer and the number of the second pads on the second wafer are 2n, n is an integer greater than 1, specifically, n is 3, that is, the first pad The six pads and the second pads are respectively used as an example to introduce the semiconductor structure and method for obtaining the resistance of the wafer-level bonding structure provided by the present invention.

[0114] First refer to Figure 9 The schematic cross-sectional structure of the first wafer is shown. The surface of the first wafer 30 has six first bonding pads 31 , which are respectively first bonding pads 311 , 312 , 313 , 314 , 315 , and 316 . Taking every two adjacent first pads as a group, the six first pads are divided into 3 groups, and the two first pads in each group are electrically connected, and the first pads between different groups Insulation between pads. For example, the first pads 311, 312 form a group and are electrically c...

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Abstract

The invention provides a semiconductor structure and a method for acquiring the resistance of a water-level bonding structure by adopting the same. The acquiring method comprises the steps of measuring the resistances of two wafers before and after bonding, and acquiring the resistance of a water-level bonding structure according to the series-parallel relationship between the resistances of the two wafers before and after bonding and the resistance of the water-level bonding structure. The acquiring method does not rely on the experience values of the resistances of a pad, a metal interconnect and a conductive plug for connecting the pad and the metal interconnect, so that the acquired resistance of the water-level bonding structure is accurate.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a method for obtaining the resistance of a wafer-level bonding structure by using the semiconductor structure. Background technique [0002] In recent years, the development of large-scale integration of semiconductor devices has driven chip designers and manufacturers to continuously seek new circuit design methods to maximize the use of chip space. A three-dimensional integrated circuit (3D Integrated Circuit, 3D IC) is a system-level architecture that is composed of multiple wafers, where each wafer contains a stack of multiple planar device layers. Based on the above advantages, 3D integrated circuits are increasingly concerned by researchers. [0003] In a typical 3D integrated circuit, copper-copper bonding (Cu Cu Bonding) is used to bond two wafers each with an active device, which is also called wafer-level (Wafer Level) ...

Claims

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Application Information

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IPC IPC(8): H01L21/60
CPCH01L24/10H01L24/81H01L24/94
Inventor 陈政张海芳戚德奎李新陈晓军刘煊杰
Owner SEMICON MFG INT (SHANGHAI) CORP
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