Frequency synthesizer for driving phase-locked loop after up-converting DDS

Abstract

The invention discloses a frequency synthesizer for driving phase-locked loop after up-converting DDS. The frequency synthesizer for driving phase-locked loop after up-converting DDS comprises a DDS circuit (5) and a phase-locked loop circuit (7); the output end of a highly stable crystal oscillator (1) is connected with the input end of a first 3 dB power divider (2); the output end of the first 3 dB power divider (2) is connected respectively with the input ends of a first direct frequency multiplier circuit (3) and a second direct frequency multiplier circuit (4); the output ends of the first direct frequency multiplier circuit (3) and a FPGA control circuit (8) are respectively connected with the input end of the DDS circuit (5); the output ends of the second direct frequency multiplier circuit (4) and the DDS circuit (5) are respectively connected with the input end of a frequency mixing filter circuit (6); and the output end of the frequency mixing filter (6) is connected with the input end of the phase-locked loop circuit (7). The frequency synthesizer for driving phase-locked loop after up-converting DDS solves the problems of the prior art such as high stray, high phase noise, large physical dimension and high power consumption exceeding standard, due to directly driving the phase-locked loop by the DDS or driving the phase-locked loop after up-converting and dividing the DDS.

Description

technical field [0001] The invention belongs to frequency synthesizer technology, in particular to a frequency synthesizer for driving a phase-locked loop after DDS up-conversion. Background technique [0002] DDS driving phase-locked loop technology is an effective way to realize small-step frequency source. However, due to the inherent spurs in the DDS phase truncation error, the spurs will deteriorate after the frequency multiplication of the phase-locked loop. In addition, the phase noise of the DDS output signal is generally worse than that of a low-phase-noise crystal oscillator. Restricted by the above two factors, it is generally difficult to obtain high phase noise and good spurious suppression at the same time by directly driving the DDS to the PLL or after the DDS is up-converted and re-divided to drive the PLL. In order to realize the level of small steps, low spurs, and low phase noise at the same time, the design method of the existing frequency synthesizer is...

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide a frequency synthesizer for driving a phase-locked loop after DDS up-conversion, to solve the problem of using DDS to directly drive the phase-locked loop or to drive the phase-locked loop after DDS up-conversion and frequency division. High spurious, high phase noise, structure size and power consumption exceed the standard and other issues

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