System and method for integrating extended double-precision 80-bit floating-point processing unit in processor

A technology of processing unit and integration method, applied in the direction of machine execution device, etc., can solve the problem of not giving FPU and processor whole point unit IU, cooperative work, etc.

Active Publication Date: 2016-08-24
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, none of these patent documents shows how to make these efficient FPUs work together with the processor integral unit IU

Method used

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  • System and method for integrating extended double-precision 80-bit floating-point processing unit in processor
  • System and method for integrating extended double-precision 80-bit floating-point processing unit in processor
  • System and method for integrating extended double-precision 80-bit floating-point processing unit in processor

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Embodiment Construction

[0057] The present invention is described in further detail below in conjunction with accompanying drawing:

[0058] refer to figure 1 and figure 2 , the integrated system of the 80-bit floating-point processing unit of extended double precision described in the present invention comprises PC, five-stage pipeline, four-stage floating-point processing pipeline and instruction pre-decoding module, and four-stage floating-point processing pipeline comprises Floating-point control module, DP2 module, DP1 module, DP0 module, FPU to be integrated and floating-point register group, the output terminal of PC is connected to the input terminal of the instruction fetch module, and the output terminal of the instruction fetch module is connected to the instruction pre-decoding module The input terminal of the instruction pre-decoding module is connected with the input terminal of the five-stage pipeline and the input terminal of the floating-point control module respectively, and the f...

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Abstract

The invention discloses an integrated system and method of an extended double-precision 80-bit floating-point processing unit in a processor. The method transforms the execution state of a multi-precision floating-point instruction into the execution state of multiple single-cycle instructions. The implementation method is to add a four-stage floating-point processing pipeline and an instruction pre-decoding module on the basis of the known five-stage pipeline processor. The instruction pre-decoding module is between the fetching stage and the decoding stage of the integral pipeline. This method can make existing embedded processors that only support single and double-precision floating-point operations have the ability to support single, double and extended double-precision (80-bit) floating-point operations, and the calculation accuracy of the embedded processor has been improved. 3 orders of magnitude, which can meet the calculation accuracy requirements of the current and future aerospace fields.

Description

technical field [0001] The invention belongs to the field of embedded microprocessors, and relates to an integrated system and method of an extended double-precision 80-bit floating-point processing unit in a processor. Background technique [0002] Engineering applications put forward higher requirements for the calculation accuracy of embedded processors. On the one hand, it is due to the application requirements of multimedia technologies such as real-time image processing and 3D technology; on the other hand, it is due to the development requirements of aviation and aerospace fields such as flight control, automatic navigation, and attitude calibration. [0003] At present, only some CISC processors of x86 architecture support 80-bit extended double-precision floating-point operations; while embedded RISC processors of typical architectures such as ARM, PowerPC, MIPS and SPARC V8 only support single- and double-precision floating-point operations. Due to the open source...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
Inventor 陈庆宇吴龙胜艾刁张辉唐威
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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