Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which can suppress position offset between semiconductor chips when projected electrodes used between the semiconductor chips are connected and laminated. In the manufacturing method of the semiconductor device according to an embodiment, position information of a third aligning mark (5C) of a second semiconductor chip (2B) which is laminated on a first semiconductor chip (2A) and a fourth aligning mark (5D) of a third semiconductor chip (2C) that moves to a second semiconductor chip (4B) is obtained. The second semiconductor chip (2B) and the third semiconductor chip (2C) are aligned and laminated based on the position information of a first aligning mark (5A) arranged on the first semiconductor chip (2A) and the third aligning mark (5C) and the fourth aligning mark (5D).

Description

[0001] This application is based on Japanese Patent Application No. 2013-61230 (filing date: March 25, 2013) and enjoys the priority thereof. This application incorporates this prior application in its entirety by reference. technical field [0002] The present invention relates to a method of manufacturing a semiconductor device. Background technique [0003] In order to achieve miniaturization and high performance of semiconductor devices, stacked semiconductor devices in which a plurality of semiconductor chips are stacked and sealed in one package are being put into practical use. In a stacked semiconductor device, it is necessary to transmit and receive electrical signals between semiconductor chips at high speed. In this case, micro bumps are used for electrical connection between semiconductor chips. The microbumps have a diameter of, for example, about 5 to 50 μm, and are formed on the surface of the semiconductor chip at a pitch of about 10 to 100 μm. In the case ...

AI Technical Summary

Problems solved by technology

This is the main reason for the increase in the number of semiconductor chips used and the decline in the manufacturing yield of multilayer stacked chips

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