Aliasing decoding method of low-density parity-check code and multi-core cooperative aliasing decoder

A low-density parity and check code technology, applied in the field of wireless communication, can solve the problems of a large number of total, difficult to further improve the throughput rate, and low efficiency of logical resource use.

Active Publication Date: 2017-01-11
TSINGHUA UNIV
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Problems solved by technology

[0012] 1. The traditional belief propagation algorithm causes the decoder to use logic resources inefficiently, and the throughput rate is difficult to further improve;
[0013] 2. The total number of RAM in the decoder is too large. When implemented in FPGA, the number of RAM occupied limits the increase in the number of parallel cores.

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  • Aliasing decoding method of low-density parity-check code and multi-core cooperative aliasing decoder
  • Aliasing decoding method of low-density parity-check code and multi-core cooperative aliasing decoder
  • Aliasing decoding method of low-density parity-check code and multi-core cooperative aliasing decoder

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Embodiment Construction

[0053] The aliasing decoding method of the low-density parity-check code (hereinafter referred to as LDPC code) proposed by the present invention, its timing is as follows image 3 shown, including the following steps:

[0054] (1) The expression of the check matrix used in the decoding process of the low-density parity-check code is:

[0055]

[0056] Among them, Π i,j It is a sub-square matrix, the number of columns of the sub-square matrix is ​​L, L=2 n , n is an integer, the sub-square matrix is ​​a square matrix of 0, or a square matrix with only one 1 in each row and only one 1 in each column, let the matrix Subsquare Π in i,j Substitute 0 or 1 to get a basis matrix The basis matrix has N columns b , the number of rows is M b , C 1 ,C 2 ,..., M respectively b The sub-matrix of L×L is denoted as a macro column, Respectively L×N b The sub-matrix of L is denoted as a macro row;

[0057] (2) Each column in the check matrix above is the variable node v of ...

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Abstract

The invention relates to a low-density parity check code aliasing and decoding method and a multi-core collaborative aliasing decoder, and belongs to the field of wireless communication. In the aliasing and decoding method, variable node decoding and check node decoding are carried out at the same time to finish low-density parity check code decoding. According to the multi-core collaborative aliasing decoder, the aliasing and decoding method is adopted, a cyclic bus is led in, a variable node arithmetic unit set, a variable node output information storage unit, a check node arithmetic unit set and a check node output information storage unit on the cyclic bus are made to work at the same time, and multi-core collaborative aliasing decoding is achieved. By means of the decoding method and the decoder, the throughput of the decoder and the logic utilization efficiency of hardware are improved; due to lead-in of the cyclic bus in the decoder, multi-core collaborative decoding is achieved, consumption of a hardware logic unit and memory blocks is lowered, and development of a low-density parity check code decoder which is high in speed and low in resource consumption is facilitated.

Description

technical field [0001] The invention relates to an aliasing decoding method of a low-density parity check code and a multi-core cooperative aliasing decoder, belonging to the field of wireless communication. Background technique [0002] Low-density parity-check codes (hereinafter referred to as LDPC codes) have error correction performance close to the limit of Shannon theory, and are very suitable for applications in broadband communication, wireless communication and other fields. According to different technical requirements, people have formulated relevant technical standards, including DVB-S2, CCSDS deep space / near-earth satellite communication, IEEE 802.16e, CMMB, etc. These technical standards adopt LDPC codes based on block and shift unit matrix construction, and the corresponding LDPC decoders can be efficiently implemented with traditional partial parallel structures. However, for LDPC codes based on block and pseudo-random interleaving unit matrix construction a...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
Inventor 殷柳国林柏洪李琪陆建华
Owner TSINGHUA UNIV
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