Semiconductor device

一种半导体、器件的技术，应用在半导体器件领域，能够解决毁坏半导体器件等问题，达到提高耐受性、减小导通电压的增大、减小电压降的效果

Inactive Publication Date: 2014-05-28
DENSO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, semiconductor devices may be destroyed

Method used

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  • Semiconductor device
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Examples

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no. 1 example ）

[0060] First, refer to figure 1 and figure 2 The structure of the semiconductor device 10 according to the present embodiment will be described.

[0061] Such as figure 1 As shown, N with a predetermined thickness in the z direction + type buffer layer 12 formed on the P + type collector layer 11 on the surface, the P + The type collector layer 11 is formed along the x-y plane and has a predetermined thickness in the x direction. N having an impurity concentration lower than that of the buffer layer 12 - Type drift layer 13 is formed on the surface of buffer layer 12 . P-type base layer 14 is formed on the surface of drift layer 13 . That is, collector layer 11 , buffer layer 12 , and drift layer 13 are stacked in this order.

[0062] A plurality of trenches 15 penetrating the base layer 14 and reaching the drift layer 13 extend in the y direction to form a stripe pattern. According to the present embodiment, trenches 15 are repeatedly formed at a regular gate pitch ...

no. 2 example ）

[0084] In the first embodiment, the length D of the communicating portion 18a in the z direction 1 is about 3.0 μm, and the length D of the bottom 18b in the z direction 2 is about 2.0 μm. In contrast, according to this embodiment, the length D 1 is approximately 2.4µm, while the length D 2 is about 1.6µm (is the length of the first embodiment D 2 0.8 times), so that the base layer 14, the emitter layer 19, and the base layer 14 form the base contact layer 20 from the surface at depths 0.8 times those of the first embodiment.

[0085] Since the structures other than the above-mentioned dimensions are the same as those of the first embodiment, detailed descriptions of other structures are omitted. In addition, regarding the advantages, because factors other than the conduction voltage are compared with the dependence of D1, D2, the base layer 14, the emitter layer 19, and the depth at which the base layer 14 forms the base contact layer 20 from the surface The turn-on volt...

no. 3 example ）

[0089] In the foregoing embodiments, the base layer 14 is located between adjacent gate trenches 18 and between adjacent emitter layers 19 . On the contrary, according to this embodiment, if Figure 8 As shown, the emitter layer 19 is continuous in the x-direction between adjacent trench gates 18 .

[0090] According to the present embodiment, emitter layer 19 is formed in the surface portion of base layer 14 and is continuous in the x direction between adjacent trench gates 18 . Like in the first embodiment, the length “C” of the base contact layer 20 is about 0.8 μm in the x direction and is spaced apart from the trench gate 18 . The thickness of the base contact layer 20 in the z direction from the base layer 14 is the same as the thickness of the emitter layer 19 . In this way, the emitter layers 19 and the base contact layers 20 are alternately arranged in the y-direction and extend from the surface of the base layer 14 to the same depth.

[0091] According to the pres...

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Abstract

In this semiconductor device, trench gates (18) are each provided with a bottom section (18b) formed in drift layer (13), and a communication section (18a) formed in communication with the bottom section from the surface of a base layer (14). The interval between adjacent bottom sections in the x direction is shorter than the interval between adjacent communication sections in the x direction. The thickness of gate insulating films (16) is thicker in the communication sections than in the bottom sections. The region between adjacent trench gates is divided, in the y direction, into an effective region (P) corresponding to an emitter layer, which serves as a source for injecting a charge to the drift layer through the application of a gate voltage, and an ineffective region (Q), which does not produce a source for injecting a charge through the application of a gate voltage. If the interval of the effective regions in the y direction is regarded as L1, the length of the communication sections in the z direction is regarded as D1, and the length of the bottom sections in the z direction is regarded as D2, L1 < =2 (D1 + D2). The x direction and the y direction are orthogonal to each other, and the z direction is orthogonal to the x-y plane, which is defined by the x direction and the y direction.

Description

[0001] Cross References to Related Applications [0002] This application is based on Japanese Patent Application No. 2011-211072 filed on September 27, 2011 and Japanese Patent Application No. 2012-196549 filed on September 6, 2012, the contents of which are incorporated by reference here. technical field [0003] The present disclosure relates to semiconductor devices having insulated gate bipolar transistors (hereinafter abbreviated as IGBTs). Background technique [0004] Semiconductor devices with IGBTs are used in electronic circuits to drive inductive loads such as motors. A semiconductor device with a typical IGBT has the following structure. [0005] N - type drift layer formed in the P + type collector layer, the P type base layer is formed on the N - type drift layer surface portion, and N + The P-type emitter layer is formed in the surface portion of the P-type base layer. By penetrating the P-type base layer and the N + The emitter layer reaches the N -...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/739
CPCH01L29/42368H01L29/7397H01L29/42376H01L29/4236H01L29/1095H01L29/0843H01L29/0834H01L29/66348
Inventor 樋口安史深津重光住友正清
Owner DENSO CORP
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