Semiconductor device manufacturing method based on self-aligned double patterning

A self-aligned double-pattern and manufacturing method technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as difficult control, complicated manufacturing process, and low yield of semiconductor devices, and achieve good connection effect

Active Publication Date: 2014-05-07
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] In order to solve the problem that in the prior art, the back-end manufacturing process (BEOL) of semiconductor devices needs to perform an end-cutting step, which makes the entire manufacturing process complex and difficult to control, resulting in low yields of semiconductor devices, the present invention provides a A method for manufacturing a semiconductor device based on a self-aligned double pattern, the method comprising:

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  • Semiconductor device manufacturing method based on self-aligned double patterning
  • Semiconductor device manufacturing method based on self-aligned double patterning
  • Semiconductor device manufacturing method based on self-aligned double patterning

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Embodiment Construction

[0034] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0035] In order to thoroughly understand the present invention, a detailed description will be provided in the following description to illustrate the method of manufacturing the semiconductor device based on the self-aligned double pattern of the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions...

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Abstract

The invention relates to a semiconductor device manufacturing method based on self-aligned double patterning. The method comprises the following steps: a back-end-of-line device is provided, and a semiconductor substrate and a dielectric layer located on the semiconductor substrate are at least comprised; the dielectric layer is patterned to remove a part of the dielectric layer and form grooves; an APF material layer is deposited and planarized to fill the grooves; the APF material layer is etched to form grooves and strip-like core lines located between the grooves; a sidewall material layer is deposited on the substrate, and then the sidewall material layer is etched to form spacing walls on sidewalls of the strip-like core lines; and the strip-like core lines are removed through etching to form a parallel strip-like pattern without performing the end cutting step separately. According to the method of the invention, a target pattern can be obtained in the back-end-of-line (BEOL) of the semiconductor device without performing the end cutting step, so the process is simple and easy to control.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular, the invention relates to a method for manufacturing a semiconductor device based on a self-aligned double pattern. Background technique [0002] For the increasing demand for high-capacity semiconductor storage devices, the integration density of these semiconductor storage devices has attracted people's attention. In order to increase the integration density of semiconductor storage devices, many different methods have been adopted in the prior art, such as by reducing the wafer size. And / or change the internal structure unit to form multiple memory units on a single wafer. For the method of increasing the integration density by changing the unit structure, attempts have been made to reduce the unit area. [0003] NAND flash memory is a better storage solution than hard disk drives. Since NAND flash memory reads and writes data in units of pages, it is suitable for stor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/31144H01L21/76802H01L21/76816
Inventor 张城龙张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP
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