Optimizing method for integrated circuit clock grid driving based on driving window

Abstract

The invention discloses a drive window-based integrated circuit clock grid drive optimization method, the implementation steps of which are as follows: divide the clock grid into multiple drive windows according to the influence range of each driver based on the low-pass filter characteristics, and traverse the drive windows , for each current drive window that is traversed, estimate the load capacitance in the current drive window, and perform bilinear interpolation look-up table to calculate all alternative drivers according to the typical input signal transition time and load capacitance under the current process. The device delay and output signal transition time; sequentially select the unit that is not greater than the maximum transition time specified by the user, the device delay is within the user-specified range, and the smallest area is used as the driver of the current drive window to complete the clock grid drive optimization. . The invention can ensure that the grid is driven reasonably without causing excessive drive, saves chip area occupation, has strong scalability, and can be conveniently combined with other grid optimization strategies.

Description

technical field [0001] The present invention relates to the field of integrated circuit (Integrated Circuit, hereinafter referred to as IC) design automation of microelectronics technology, and in particular to an integrated circuit clock grid drive optimization method based on a drive window. Background technique [0002] In the physical design of semi-custom integrated circuits, devices are basically selected from the cell library provided by the process manufacturer, so the timing and physical indicators of the cells need to be specially considered to meet various design requirements. The timing of the device mainly refers to the device delay and the output signal transition time, and the physical index of the device mainly concerns the size of the unit area. [0003] The device delay indicates the time elapsed when the signal passes through a logic gate. Generally, it is defined as the time required for a 50% change in the input signal voltage to a 50% change in the outp...

AI Technical Summary

Problems solved by technology

In today's large-scale chip design, there are often a series of negative effects such as wiring congestion caused by driver unit congestion, difficulty in timing convergence, excessive local voltage drop, and excessive local power consumption density. Inappropriate choice of type is also an important reason

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