MOSFET structure and manufacturing method thereof

Abstract

The invention provides an MOSFET manufacturing method. The MOSFET manufacturing method includes the following steps that: A. a substrate (100), source and drain regions (200), a pseudo gate stack layer (150), interlayer dielectric layers (300) and lateral walls (160) are provided; B. the pseudo gate stack layer (150) is removed, such that a pseudo gate vacancy is formed; C. tilted ion implantation is performed on a semiconductor structure, such that a carrier scattering region (400) is formed, wherein the carrier scattering region (400) is located below the surface of the semiconductor structure at one side of a drain end; and D. a gate stack layer (500) is deposited in the pseudo gate vacancy. According to a method for reducing hot carrier transition probability provided by the invention, a scattering impurity is implanted into a channel material which is adjacent to one side of the drain end, wherein the scattering impurity is a non-ionized impurity, and the probability of hot carriers of being scattered in a pinch-off region can be increased, and therefore, a resistance borne by the carriers when the carriers move in the pinch-off region can be increased, the energy of the hot carriers can be reduced, and the number of hot carriers that enter the gate dielectric layers and the probability for the hot carriers to enter the gate dielectric layers are decreased.

Description

technical field [0001] The invention relates to a MOSFET structure and a manufacturing method thereof. More particularly, it relates to a MOSFET structure for reducing the number of hot electrons in a channel near the drain and a method of manufacturing the same. technical background [0002] When the MOSFET is in the saturation region, the channel inversion layer is partially pinched off, that is, the inversion carrier concentration on the channel surface near the drain end is very small, and the resistance is large. According to the series voltage division relationship, the voltage in the channel region is mostly Falling on the pinch-off region, a large electric field is generated in the pinch-off region. When the anti-type carriers in the channel region move to the boundary of the pinch-off region under the action of the electric field, they will be accelerated by the electric field of the pinch-off region, and will be quickly swept to the drain end. During this process,...

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Problems solved by technology

[0003] As the voltage between the source and drain increases, the electric field where the carriers in the pinch-off region is also increases, so the electrons can obtain higher speed and greater energy, and generate a certain number of hot carriers. When the electric field in the pinch-off region increases to a certain extent, these hot carriers have a certain probability to cross the barrier between the channel and the gate dielectric layer and enter the gate dielectric layer, thereby introducing defects and traps in the gate dielectric layer , affecting device performance

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