Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Self-inspection method and device of inter integrated circuit host and host

A technology of internal integrated circuits and hosts, applied in the field of communication, can solve problems that cannot be performed in real time

Active Publication Date: 2014-01-22
XFUSION DIGITAL TECH CO LTD
View PDF3 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In order to solve the problem that the existing technology cannot be carried out in real time and cannot avoid repeated replacement of the I2C host controlling the I2C bus, the embodiment of the present invention provides a self-test method, device and host for an internal integrated circuit I2C host

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Self-inspection method and device of inter integrated circuit host and host
  • Self-inspection method and device of inter integrated circuit host and host
  • Self-inspection method and device of inter integrated circuit host and host

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0084] The embodiment of the present invention provides a self-test method of an I2C master, which can be executed when a standby I2C master establishes a connection with the I2C bus, see figure 2 , the method includes:

[0085] Step 101: the I2C master detects whether the I2C bus is busy.

[0086] Step 102: When the I2C bus is busy, receive a data packet transmitted on the I2C bus, and check whether the link of the I2C host is normal according to the data packet.

[0087] In the embodiment of the present invention, when the I2C bus is busy, the data packet transmitted on the I2C bus is received, and the link of the I2C host is detected according to the data packet, so the self-test of the I2C host does not need to wait until the I2C bus is idle. The embodiment of the present invention can be carried out in real time, avoiding the failure of the I2C master currently controlling the I2C bus existing in the prior art during the process of the I2C master waiting for self-inspec...

Embodiment 2

[0089] The embodiment of the present invention provides a self-test method of an I2C master, which can be executed when a standby I2C master establishes a connection with the I2C bus, see image 3 , the method includes:

[0090] Step 201: The I2C master detects whether the I2C bus is busy.

[0091] Specifically, this step 201 may include: detecting whether there is a level change on the SCL line within a period of a preset standard clock signal; if there is a level change on the SCL line within a period of a preset standard clock signal, Then the I2C bus is busy; if there is no level change on the SCL line within a period of a preset standard clock signal, the I2C bus is idle.

[0092] It should be noted that, according to the I2C protocol, when data transmission is performed on the I2C bus, that is, when the I2C bus is busy, there will be high and low levels on the SCL line, and the period of the level change is the period of the preset standard clock signal (The time interva...

Embodiment 3

[0124] The embodiment of the present invention provides a self-checking method of the I2C host, which is an improvement on the second embodiment. This method can be executed when the standby I2C host establishes a connection with the I2C bus. See Figure 5 , the method includes:

[0125] Step 301: The I2C master detects whether the I2C bus is busy. When the I2C bus is idle, execute step 302; when the I2C bus is busy, execute step 303.

[0126] Optionally, this step 301 may be the same as step 201 in Embodiment 2, which will not be described in detail here.

[0127] Step 302: Control the I2C bus, send a preset data packet to the I2C slave, and judge whether the I2C master can control the I2C bus according to whether a response signal sent by the I2C slave is received.

[0128] Optionally, this step 302 may include: when receiving the response signal sent by the I2C slave, determine that the I2C master can control the I2C bus; when not receiving the response signal sent by the...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a self-inspection method and device of an inter integrated circuit host and the host, and belongs to the technical field of communication. The method comprises the steps that the I2C host detects whether an I2C bus is busy; when the I2C bus is busy, data packets transmitted on the I2C bus are received, and whether a link of the I2C host is normal is detected according to the data packets. According to the method, when the I2C bus is busy, the data packets transmitted on the I2C bus are received, whether the link of the I2C host is normal is detected according to the data packets, and therefore it is not necessary to wait to conduct self-inspection of the I2C host when the I2C bus is free, self-inspection can be conducted in real time, and the problem that when the I2C host waits for self-inspection, the I2C host controlling the I2C bus at present breaks down and cannot be replaced by a spare I2C host, and therefore the I2C host controlling the I2C bus is changed repeatedly is solved.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a self-checking method, device and host for an internal integrated circuit host. Background technique [0002] The I2C (Inter Integrated Circuit, internal integrated circuit) bus is a bus standard widely used in the field of microelectronics communication control, and is used to connect I2C masters, I2C slaves and other devices. The I2C master is a device that initiates transmission, generates a clock signal, and terminates transmission, and can become a device that controls the I2C bus. The I2C slave is a device addressed by the I2C master. [0003] Usually there is only one master on the I2C bus. If there are two I2C masters connected to the I2C bus, one is the I2C master currently controlling the I2C bus, and the other is the standby I2C master. Taking the first I2C master as the I2C master currently controlling the I2C bus, and the second I2C master as the backup I2C...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F11/267
Inventor 郭中天种锋生黄平
Owner XFUSION DIGITAL TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com