Array substrate and manufacturing method thereof

Abstract

The invention discloses an array substrate and a manufacturing method thereof. The problems that signal lines in an existing array substrate are all placed on the same layer, so that equal resistance between the signal lines is achieved, part of the signal lines are horizontally bent, and accordingly signal line density of a wiring zone is small, the drive number is large, and cost is high are solved. The array substrate comprises a plurality of wiring zones arranged on a non-displaying zone, a plurality of signal lines are arranged in the wiring zones, at least part of the signal lines in each wiring zone are formed by leading wires in different layers in a series-connecting mode, and the resistance difference between any two signal lines in the same wiring zone is in the threshold value range. According to the array substrate and the manufacturing method thereof, traditional signal lines placed in one layer of the array substrate are changed to the signal lines placed between the multiple layers, so that the fact that the resistance difference between the signal lines is smaller than the threshold value and the bending radius of the signal lines is small is facilitated, signal line concentrating density is large, the drive number is lowered, and the purpose of cost lowering is achieved.

Description

technical field [0001] The present invention relates to the display field, in particular to an array substrate and a manufacturing method thereof. Background technique [0002] Structures such as gate lines, data lines, thin film transistors, and pixel electrodes are arranged on the array substrate; the above structures are all made of different layers of conductive materials. Generally, the array substrate has a layered structure including a gate metal layer forming a gate, a source-drain metal layer forming a source and drain of a thin film transistor, and a pixel electrode layer forming a pixel electrode. Some array substrates also include a common electrode layer forming a common electrode. Wherein, the gate line is connected to the gate of the thin film transistor; the data line is connected to the source of the thin film transistor; the gate line is used to turn on the thin film transistor, and the data line is used to input a voltage signal to the pixel electrode thr...

AI Technical Summary

Problems solved by technology

In order to make the signal line 011 and the signal line 012 form an equal-resistance conduction path, the signal line 012 is made into a zigzag shape, but the formation of the zigzag line will cause the width of the wiring area occupied by the signal line to widen

In the prior art, when folded lines are formed on the same layer of the array substrate, the width occupied by the signal line 012 is d, so that the number of signal lines that can be accommodated in the same area of ​​the wiring area is reduced, which in turn leads to an increase in the number of drivers (COF, etc.) , the increase in the number of drivers will inevitably lead to an increase in the number of driver ICs, which ultimately leads to an increase in cost

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