Chip structure and chip packaging structure

Abstract

Provided are a chip structure and a chip packaging structure. The chip packaging structure comprises at least two chip structures and conductive adhesives located in conductive grooves, wherein the side walls of the chip structures are provided with the conductive grooves, the chip structures are stacked, the conductive grooves of the stacked chip structures correspond in position, and circuits in the stacked chip structures are electrically connected through the conductive adhesives. Due to the fact that the conductive grooves are formed in the side walls of insulating layers, the conductive adhesives formed in the conductive grooves later cannot be in direct contact with chips, and short-circuit phenomena cannot occur; due to the fact that the conductive grooves and contact welding plates are connected through metal interconnection layers on the surfaces of the insulating layers, the insulating layers cannot influence layout design of other metal interconnection structures in the chips, the practice that extra metal interconnection structures are designed due to positions of the contact welding plates is needless, the chip area occupied by the metal interconnection structures can be saved, and the component integration degree of the chips can be beneficially improved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a chip structure and a chip packaging structure. Background technique [0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices has become very small. It is becoming more and more difficult to increase the number of semiconductor devices in a two-dimensional chip structure. Therefore, three-dimensional packaging, that is, stacking and packaging multiple chips, has become A method that can effectively improve chip integration. Current three-dimensional packaging includes die stacking based on wire bonding, package stacking and three-dimensional stacking based on through silicon vias (Through Silicon Via, TSV). Among them, the three-dimensional stacking technology using through-silicon vias has the following three advantages: (1) high-density integration; (2) greatly shortening the length of electrical interconnections, ...

AI Technical Summary

Problems solved by technology

[0003] However, since the three-dimensional stacking technology based on through-silicon vias needs to form several through-silicon vias in the chip, the chip needs to be thinned when forming the through-silicon vias, but the mechanical strength of the thinned chip is poor, and it is easy to deform or even break ; Simultaneously because the metal material filled in the said TSV is copper, the thermal expansion coefficient of the copper and the silicon substrate of the chip is very different, so a stress zone will be formed near the chip position of the TSV, and the stress will affect the semiconductor device Therefore, semiconductor devices cannot be formed in the stress region, which will cause a waste of chip area; at the same time, due to the high process requirements for forming through-silicon vias, the process cost is relatively high

Images