A clock multiple selection one circuit and multiple selection one method
A clock selection and clock selector technology, applied in the direction of synchronous pulse counters, etc., can solve the problems of design without outstanding anti-SEU, increase system cost, complexity and coupling, and cannot independently select clocks, and achieve enhanced reliability. , the effect of improving system performance and reliability, and reducing system cost
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[0043] The invention provides a clock multiple selection circuit and multiple selection method. The present invention will be described in further detail below in conjunction with the accompanying drawings.
[0044] figure 1 Shown is a structural block diagram of a clock multiple selection circuit, which is composed of a clock counter module 100, a clock selection signal generator module 300 and a clock selector module 200 in series;
[0045] Assuming that the number of input clock signals is m and m≥2, the first clock signal to the mth clock signal are recorded as clk1 to clkm respectively. For the convenience of explanation, the clock counters corresponding to each clock signal are taken as quaternary cycle counters, each The counting upper limit value of the detected clock invalid counter in the sub-state machine is set to 7;
[0046] Described clock counter module comprises m quaternary counter modules, is used for carrying out the cycle count from 0 to 3 to each road in...
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