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Method and system for adjusting capacity of a process stage with residence time limitation

A technology of dwell time and stage, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems affecting yield, affecting wafer yield, etc., and achieve the effect of avoiding the impact of yield

Active Publication Date: 2015-12-02
SHANGHAI HUALI MICROELECTRONICS CORP
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AI Technical Summary

Problems solved by technology

In this case, if there is a problem with any of the subsequent process production machines in these 3 process steps, the products cannot be processed effectively and in time, even in a fully automated production workshop, a large number of products will accumulate at a certain station and exceed the specified stay time, thus affecting wafer yield
[0004] Therefore, there is a need for a method and system for dynamically adjusting the production capacity of a process stage with a residence time limit based on a pre-analyzed output, which can balance the production capacity and load of each process stage, and avoid the impact of the product being too long in the residence time with a residence time limit. Yield, to achieve a win-win situation in production capacity and quality

Method used

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  • Method and system for adjusting capacity of a process stage with residence time limitation

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Embodiment Construction

[0023] In order to rationally configure the production capacity of each process stage and achieve a win-win situation for both quality and production capacity, this invention provides a method for adjusting the production capacity of a process stage with a residence time limit. Please refer to figure 1 Shown is a schematic flow diagram of a method for adjusting the capacity of a process stage with a residence time limitation according to an embodiment of the present invention, comprising:

[0024] Step S1, obtaining the current process stage with a residence time limit, obtaining the specified residence time of the current process stage, production capacity, and the number of products currently waiting to be produced;

[0025] Step S2, obtaining the maximum residence time of the current process stage based on the specified residence time, production capacity, and the number of products currently waiting to be produced in the current process stage;

[0026] Step S3, if the maxi...

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Abstract

The invention provides a method and a system for adjusting capacity of process stages with residence time limitation. The method comprises the steps that the current process stage with the residence time limitation is obtained; specified residence time, the capacity and the number of the current products waiting for production of the current process stage are obtained; the maximum residence time of the current process stage is obtained; if the maximum residence time is greater than the specified residence time, the capacity of the previous process stage is reduced; contrarily, the predicted maximum residence time of the current process stage after the capacity of the previous process stage is increased is predicted; if the predicted maximum residence time is less than or equal to the specified residence time, the capacity of the previous process stage is increased; and contrarily, the capacity of the previous process stage is maintained. According to the method and the system, the capacity of the relevant process stages can be adjusted automatically, and the capacity among the process stages is balanced, so that a yield is prevented from being influenced, and mutual benefits of the capacity and the quality are achieved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a system and method for dynamically adjusting production capacity of a process stage with a residence time limit based on pre-production analysis. Background technique [0002] With the continuous improvement of integrated circuit technology and production costs, wafer manufacturers often increase the number of tape-outs to obtain more economic benefits. Therefore, it is necessary to pay more attention to the control of wafer defects, so as to avoid problems in a certain process from affecting more wafer production and causing huge economic losses. For the post-stage copper process process, including the copper barrier layer process stage to the copper metal layer process stage, the copper metal layer process stage to the copper chemical polishing layer process stage, the copper chemical polishing layer process stage to the chemical vapor deposition layer process stage, in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/67
Inventor 朱陆君倪棋梁龙吟陈宏璘王洲男
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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