Clock supply device and method thereof

Abstract

Disclosed are a clock pulse supply device and a method of the clock pulse supply device. The device comprises a frequency generating unit and a control unit. The frequency generating unit is used for responding a pattern signal to decide whether vibration amplitude of a clock pulse signal is first vibration amplitude or second vibration amplitude and converting an outer vibration signal to the clock pulse signal. The control unit receives the clock pulse signal and is used for responding a system status signal to output the pattern signal. When the control unit judges that the clock pulse signal is stable vibration, the clock pulse signal is supplied outside by the control unit. If the system status signal is a power-on signal, the first vibration amplitude is used as the vibration amplitude of the clock pulse signal. If the system status signal is a power-off signal, the second vibration amplitude which is smaller than the first vibration amplitude is used as the vibration amplitude of the clock pulse signal.

Description

technical field [0001] The present invention relates to an electronic clock technology, in particular to a clock supply device suitable for an electronic clock system and a method thereof. Background technique [0002] figure 1 is a schematic diagram of a typical electronic clock system 100 . Please refer to figure 1 . A general electronic device is configured with an electronic clock system 100 , and the electronic clock system 100 provides a clock signal CLK required by the electronic device to make the electronic device operate normally. The electronic clock system 100 includes a frequency generation module 10 , a phase locked loop (PLL) 20 , a counter 30 , a crystal oscillator 40 and a battery BAT. The electronic clock system 100 utilizes the quartz oscillator 40 and the frequency generating module 10 to generate a clock signal CLK of 32,768 Hz. The phase-locked loop 20 multiplies the frequency of the clock signal CLK for use by the circuits at the back end. The co...

AI Technical Summary

Problems solved by technology

However, if the amplitude of the voltage becomes smaller, the obvious disadvantage is that the noise becomes larger

Noise or jitter will cause the duty cycle of the clock signal CLK to be inaccurate

Therefore, under the framework of the typical electronic clock system 100, the frequency-multiplied clock output by the phase-locked loop 20 will be abnormal in order to save power.

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