Metal gate stack having TIALN blocking/wetting layer

Abstract

A metal gate stack having a TiAlN blocking / wetting layer, and methods of manufacturing the same, are disclosed. In an embodiment, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting / blocking layer disposed over the work function layer, wherein the multi-function wetting / blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting / blocking layer.

Description

technical field [0001] The present invention relates to the field of semiconductors, and more particularly, to metal gate stacks with TiAlN barrier / wetting layers. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and similar developments in processing and manufacturing ICs are required for these advancements to be realized. During the evolution of integrated circuits, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component (or line) producible using a fabrication process) has decreased. Typically, this scaling down process benefits by increasing production efficiency a...

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Problems solved by technology

This scaling down process also increases the complexity of processing and manufacturing ICs, and similar developments in processing and manufacturing ICs are required to achieve these advances

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