JTAG (joint test action group) main controller and realization method of JTAG main controller

Abstract

The invention relates to a JTAG (joint test action group) main controller and a realization method of the JTAG main controller. The JTAG main controller comprises a JTAG signal generator. The JTAG signal generator obtains external HOST instructions, in addition, the HOST instructions are analyzed to obtain IR (instruction register) instructions or DR (data register) data, so corresponding JTAG interface signals are generated according to IR instructions or DR data, and a target chip is driven through the JTAG interface signals. The JTAG main controller and the realization method have high execution instruction efficiency, and can be applied into a JTAG device.

Description

technical field [0001] The invention relates to the field of electronics, in particular to JTAG devices. Background technique [0002] As an interface standard of IEEE, JTAG interface plays an important role in the testing, simulation, debugging and other aspects of integrated circuits. Most existing advanced devices support the JTAG protocol, such as DSP, FPGA and other devices. [0003] The standard JTAG interface includes a test clock input signal TCK, a test data input signal TDI, a test mode selection signal TMS, a test data output port TDO, and an optional test reset input signal TRST. [0004] The internal logic of the JTAG device is realized by a TAP state machine, figure 1 A schematic diagram of the state transition of the TAP state machine of the JTAG device specified in the IEEE1149.1 standard is shown. Such as figure 1 As shown, the TAP state machine includes two branches, namely a command register access (IR Access) branch and a data register access (DR Acce...

AI Technical Summary

Problems solved by technology

[0007] Traditional JTAG master controllers are implemented by MIPS, ARM and other processors. Since the functions executed by MIPS and ARM systems are implemented by software, and MIPS and ARM’s own instructions are used to complete specific functions, a JTAG instruction needs Use multiple MIPS instructions to simulate, and because the completion of tasks in MIPS and ARM systems is completed through scheduling, the JTAG signals (ie, TCK, TMS, TDI, etc. signals) generated by them are irregular, and the delay between the two instructions Larger, which is extremely unfavorable for chip testing

Especially when performing performance tests on JTAG interface control circuits, MIPS and ARM processors cannot generate high-frequency test clocks, which affects test results

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