Design and method of domain layout of 14-bit integrated circuit DAC (Digital to Analog Converter) current source array

Abstract

The invention discloses design and a method of domain layout of a 14-bit integrated circuit DAC (Digital to Analog Converter) current source array. In the design of the domain layout of the 14-bit integrated circuit DAC (Digital To Analog Converter) current source array, a main array formed by orderly arranging a plurality of current source is comprised; the main array is divided into four main quadrants by a vertical centerline and a horizontal centerline; the current source arrays of the four main quadrants are arranged in a star-like symmetrical manner based on a center; each main quadrant is divided into four auxiliary quadrants by a vertical centerline and a horizontal centerline, and four auxiliary quadrants are arranged in a star-like symmetrical manner based on a center. Specifically, a two-layer tree-like structure is adopted, bidimentional two-step symmetrical layout is achieved, layers are relatively independent, and quadrants are relatively independent; when number input codes are increased from full 0 to full 1 and the current sources are sequentially opened, the structure can well eliminate gradient error, symmetry error and immediate technology error and has good heat-resistant gradient effect. The design has the characteristics of good monotonicity, offset error, differential and integral linearity, spurious-free dynamic range and signal to noise ratio.

Description

technical field [0001] The invention relates to a D / A converter, in particular to a 14-bit integrated circuit DAC current source array and a layout method thereof. Background technique [0002] DAC is Digital-to-Analog Converter (Digital-to-Analog Converter). The research and application of this module mainly focus on the research of current source structure. It directly affects the performance index of the module, which is mainly based on the 0.13um process gradient limit factor provided by Foundry. It is composed of 3.3 (V) PMOSFET, which has high conversion accuracy, fast frequency switching, consistent wiring, good linearity, and matching degree High advantages, so it is widely used in electronic systems such as radar, communication, and electronic countermeasures that require high sensitivity. [0003] The current source matching error is mainly manifested in the layout design: [0004] (1) Random matching error. The random error is determined by the matching characte...

AI Technical Summary

Problems solved by technology

[0007] like image 3 The layout of the traditional current source array layout is shown, which is a 5+5 segmented structure. Most designers arrange the high bit line in a trapezoidal layout on both sides of the LSB line, and the layout sequence takes into account the symmetry error caused by the opening of the current source. And the gradient error can reduce the tube mismatch to a certain extent, but this structure focuses on the symmetry of the planar structure, and does not consider the spatial distribution, and the conversion accuracy of this structure is not very high

When the conversion precision is above 12 bits, this structure can no longer meet the requirements of high conversion precision and high speed

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