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Method and system for scheduling threads in a processor

A processor and thread technology, applied in electrical digital data processing, instruments, program control design, etc., can solve problems such as being unsuitable for multi-threaded systems, and achieve the effects of avoiding insufficient threads, reducing packaging costs, and increasing reliability.

Active Publication Date: 2012-07-11
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This solution uses a mix and match of different workloads to manage temperature and is not suitable for multi-threaded systems

Method used

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  • Method and system for scheduling threads in a processor
  • Method and system for scheduling threads in a processor
  • Method and system for scheduling threads in a processor

Examples

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Embodiment Construction

[0031] According to a preferred embodiment of the present invention, a method for directing OS thread scheduling in a multi-core and multi-threaded microprocessor is provided. The method includes selecting a subset of different active threads of a running application / job to run in a future context switch time period based on their predicted power consumption relative to a last context switch (CS). As is well known in the art, a "context switch period" or "context switch interval" means a period of time during which a set of applications or threads are scheduled to run on a computer processor, eg, by the operating system.

[0032] For ease of description, time-related terms (such as "next", "future", "last time", "previous") will be used herein to describe the relationship between a context switching interval and another context switching interval. It will be understood that these time-related terms are intended to include successive time-switching intervals according to a time...

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PUM

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Abstract

The invention provides a method for guiding OS thread scheduling in multi-core and / or multi-threaded microprocessors. The method includes: determining, for each thread among the active threads, the power consumed by each instruction type associated with an instruction executed by the thread during the last context switch interval; determining for each thread among the active threads, the power consumption expected for each instruction type associated with an instruction scheduled by said thread during the next context switch interval; generating at least one combination of N threads among the active threads (M), and for each generated combination determining if the combination of N threads satisfies a main condition related to the power consumption per instruction type expected for each thread of the thread combination during the next context switch interval and to the thread power consumption per instruction type determined for each thread of the thread combination during said given context switch interval; and selecting a combination of N threads to be scheduled from combinations that satisfy a main condition.

Description

technical field [0001] The present invention relates generally to processor technology, and more particularly to methods and systems for scheduling threads in multi-threaded or multi-core processors. Background technique [0002] Over the past few years, the power consumption of computers has become a major concern in the design of integrated chips (ICs) and in particular microprocessors. Temperature is directly related to the energy dissipated, which in turn is directly proportional to power consumption over a time interval. The temperature level determines the cooling rate and packaging technology selection. For example, in recent years, companies have been considering fluid cooling subsystems for their high power dissipating machines. Other aspects related to power dissipation and temperature levels are the reliability of the IC and the cost of packaging. [0003] The reliability of an IC depends on how much and how often the IC is heated. In an IC production line, IC...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50
CPCY02B60/144G06F9/4893G06F9/50Y02D10/00
Inventor H.E.艾尔希希尼A.T.赛伊德加梅尔艾尔丁
Owner INT BUSINESS MASCH CORP
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