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General rapid decoding coprocessor of quasi-cyclic low density parity check code

A low-density parity and coprocessor technology, applied in the field of channel coding and decoding, can solve problems such as low decoding efficiency and scattered storage resource allocation, and achieve the effect of improving decoding efficiency

Active Publication Date: 2012-05-30
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

[0008] However, there are two problems in the traditional general-purpose decoder: one is that the allocation of storage resources is relatively scattered, requiring multiple independent storage modules to support the decoding operation; the other is the sum operation (VNU) and product operation ( CNU) are alternately performed, and the sum-product operation unit is alternately in an idle state, and the decoding efficiency is not high

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  • General rapid decoding coprocessor of quasi-cyclic low density parity check code
  • General rapid decoding coprocessor of quasi-cyclic low density parity check code
  • General rapid decoding coprocessor of quasi-cyclic low density parity check code

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Embodiment 1

[0055] Embodiment 1: Example of a serial operator

[0056]Serial operators perform sum and product operations in serial cascade

[0057] Λ' i，j_k =Λ j_k -R i，j_k

[0058] R i , j _ k ′ = min j ′ ∈ N ( i ) \ j ( Λ i , j ′ _ k ′ )

[0059] Λ j_k = Λ' i，j_k +R i，j_k

[0060] Its structure is as Figure 5 shown. Since the serial operator can only receive one sum information at a time, its operation sh...

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Abstract

The invention discloses a general rapid decoding coprocessor of a quasi-cyclic low density parity check code. Through a configuration unit, configuration of a matrix characteristic of a low density check code is realized. Through a monoblock wide-mouth memory unit, unified storage of channel information and decoding external information is realized. Unified format parallel scheduling of various different verification matrix decoding data is completed through an operation input control unit and an operation output control unit. Sum operation and product operation of parallel scheduling data with a unified format are completed at one time through a multi-path parallel operation unit, and general rapid decoding is realized. By employing the coprocessor of the present invention, by only using one block of storage resource, concentration management of the storage resource is realized; an operation unit can complete the sum operation and the product operation at one time and is suitable for sum nodes with various different dimensions and product nodes with various different dimensions; through the configuration unit, information of various different quasi-cyclic low density check codes can be stored, and general co-processing decoding of various different codes is realized.

Description

technical field [0001] The invention relates to the technical field of channel coding and decoding, in particular to a general fast decoding coprocessor for quasi-cyclic low-density check matrix codes. Background technique [0002] Channel coding technology, as the basic technology to ensure the reliable transmission of communication system, has developed rapidly in the past ten years. A large number of channel coding technologies represented by Turbo codes and low-density parity-check codes (LDPC codes) can approach the theoretical limit one after another. It has been discovered and studied deeply, among which LDPC code has received special attention in recent years. In the formulation of various communication standards, it is widely considered to be able to replace Turbo code and become the main channel coding scheme of the next generation communication system. [0003] LDPC code has been widely favored for its excellent performance close to Shannon's limit and its decodin...

Claims

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Application Information

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IPC IPC(8): H04L1/00
Inventor 管武李婧梁利平
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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